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mithro /ixo-usb-jtag

Star70

usb-jtag - Altera USB Blaster Emulation with a FX2

fpga xilinx altera usb-devices openocd jtag numato-opsis digilent-atlys cypress-fx2 ezusb digilent opsis numato urjtag

UpdatedJul 7, 2021
C++

Digilent /WaveForms-SDK-Getting-Started-PY

Star45

Demo package for the WaveForms SDK Getting Started guide and multiple test scripts for different instruments.

waveforms digilent

UpdatedJan 22, 2025
Python

This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.

fpga rocket-chip xilinx fpga-soc risc-v xilinx-fpga bitstream digilent e300 sifive artix-100t sifive-freedom arty-a7 artix-35t

UpdatedJan 23, 2024
Scala

mariusgreuel /dwfpy

Star24

Digilent WaveForms for Python

python waveforms digilent ad2 analog-discovery analog-discovery-2 ad3 digital-discovery analog-discovery-3

UpdatedFeb 21, 2025
Python

lvgl /lv_port_xilinx_zedboard_vitis

Sponsor

Star22

This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals

embedded usb tcp amd mouse freertos ntp xilinx vivado touchscreen zedboard vga digilent lvgl vitis

UpdatedOct 12, 2023
C

charkster /spi_slave_verilog

Star15

SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs

spi xilinx-fpga digilent

UpdatedDec 15, 2019
Verilog

mattuna15 /merlin

Star13

Learn how to create your own 32-bit system from scratch.

fpga hardware vivado retrogaming xilinx-fpga 68k digilent 68000 arty gcc-cross-compiler gameduino 68k-assembly

UpdatedFeb 15, 2022
Assembly

pavel-demin /eclypse-z7-notes

Star12

Notes on the Eclypse Z7 development board

fpga zynq dsp tcl verilog xilinx sdr vivado digilent vitis eclypse-z7

UpdatedFeb 27, 2025
C

knack-supply /curve-tracer

Star10

A companion app for AD2 curve tracer

electronics oscilloscope digilent electronics-lab

UpdatedFeb 8, 2020
Rust

adwuard /xSynth-go

Star6

Portable FPGA based Synthesizer/DSP processor

fpga hardware signal-processing dsp synthesizer diy digital-signal-processing digilent diy-electronics xfm2

UpdatedJun 29, 2024
Hack

charkster /cmod_a7_spi_sram

Star6

SPI slave to External SRAM interface for Cmod A7

spi sram xilinx-fpga digilent spi-slave cmod-a7

UpdatedOct 22, 2022
SystemVerilog

romybompart /Basys3-clock-alarm-with-buzzer

Star6

Digital clock implemented in vhdl for the Basys 3 Board from Digilent.

clock vhd buzzer digit digital-clock basys3 digilent vhdl-code basys3-fpga basys3-clock-alarm buzzer-termination

UpdatedDec 14, 2020
VHDL

Digilent /WaveForms-SDK-Getting-Started-Cpp

Star5

Demo package for the WaveForms SDK Getting Started guide and multiple test scripts for different instruments.

waveforms digilent

UpdatedOct 4, 2022
C++

cajt /cmod-a7-35t_leon3

Star5

GRLIB GPL support for Digilent CMOD A7 35T board

fpga vhdl sparc fpga-soc digilent cmod leon3 grlib artix-7

UpdatedJan 5, 2020
VHDL

mariusgreuel /Analog-Discovery-Adapter

Star5

Pin Header Adapter for Analog Discovery USB Oscilloscope

waveforms digilent ad2 analog-discovery analog-discovery-2

UpdatedMar 19, 2022

DiegoRosales /Zybo_Sampler

Star4

Audio Sampler for Zybo

audio fpga rtl verilog fpga-soc xilinx-fpga embedded-c digilent digilent-zybo

UpdatedFeb 6, 2022
C

pConst /xilinx_max_power

Star4

Stress test power subsystem of your Xilinx FPGA board

development board fpga test power verilog xilinx systemverilog cooling soc shift-register digilent arty ultrascale zinq

UpdatedApr 8, 2018
SystemVerilog

SnrNotHere16 /Asynchronous-FIFO

Star4

An FPGA implementation of Cummings' Asynchronous FIFO

fpga rtl verilog xilinx synthesis systemverilog fifo uvm xilinx-fpga xilinx-vivado digilent hardware-description-language nexys4ddr universal-verification-methodology fpga-programming digilent-nexys-4-board synthesizable asynchronous-fifo uvm-verification register-transistor-level

UpdatedApr 14, 2022
SystemVerilog

asankaSovis /Bidirectional_Transmitter

Star4

📡 This project was intended to develop a bidirectional transmitter and reciever device that uses Visible Light Communication (VLC) technology to transmit and recieve data from one device to another. In its basic form, data is transmitted as pulses of light where on means bit 1 and off means bit 0.

fpga amd uart-protocol serial-communication digilent cora zynq-7000 transciever fpga-programming

UpdatedApr 27, 2023
HTML

embed-dsp /ed_digilent_adept

Star4

Install of Digilent Adept 2 Runtime and Utilities

digilent adept

UpdatedMay 18, 2024
Makefile

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digilent

Here are 50 public repositories matching this topic...

mithro /ixo-usb-jtag

Digilent /WaveForms-SDK-Getting-Started-PY

hex-five /multizone-fpga

mariusgreuel /dwfpy

lvgl /lv_port_xilinx_zedboard_vitis

charkster /spi_slave_verilog

mattuna15 /merlin

pavel-demin /eclypse-z7-notes

knack-supply /curve-tracer

adwuard /xSynth-go

charkster /cmod_a7_spi_sram

romybompart /Basys3-clock-alarm-with-buzzer

Digilent /WaveForms-SDK-Getting-Started-Cpp

cajt /cmod-a7-35t_leon3

mariusgreuel /Analog-Discovery-Adapter

DiegoRosales /Zybo_Sampler

pConst /xilinx_max_power

SnrNotHere16 /Asynchronous-FIFO

asankaSovis /Bidirectional_Transmitter

embed-dsp /ed_digilent_adept

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