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fpga controller vhdl accelerometer spi ghdl spi-master spi-slave cyc1000 spi-loopback spi-controller

Star170

SPI master and SPI slave for FPGA written in VHDL

UpdatedApr 24, 2021
VHDL

jakubcabal /uart-for-fpga

fpga simulation controller vhdl uart ghdl wishbone uart-controller wishbone-bus cyc1000 uart-loopback

Star95

Simple UART controller for FPGA written in VHDL

UpdatedAug 7, 2021
VHDL

jakubcabal /rmii-firewall-fpga

fpga quartus-prime nios2 sdram sdram-controller cyclone-10lp cyc1000

Star22

RMII Firewall FPGA

fpga firewall vhdl ethernet wishbone-bus rmii cyc1000

UpdatedDec 2, 2019
VHDL

MinatsuT /CYC1000_SDRAM

Star13

A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

UpdatedJul 8, 2021
Verilog

jakubcabal /sdram-tester-fpga

python fpga vhdl sdram sdram-controller cyc1000 measures-throughput sdram-tester

Star10

SDRAM Tester implemented in FPGA

UpdatedMay 1, 2021
VHDL

Cellgalvano /vhdl_rgbmatrix_driver

Star8

A simple driver for RGB Led Panels of different sizes

fpga vhdl spi cpld hub75 rgb-led-matrix cyc1000 max1000 arrow-european-fpga-contest

UpdatedApr 11, 2020
C++

jakubcabal /cyc1000-rsu

Star7

The CYC1000 FPGA Remote System Upgrade project

fpga vhdl uart rsu cyc1000 bitstream-update cyclone10lp

UpdatedAug 8, 2021
VHDL

AtlasFPGA /BASECARRIERBOARDATLAS

Star3

Base carrier board for ATLAS, cost reduced version.

kicad cyc1000 max1000 pi-pico pi-pico-w

UpdatedDec 11, 2023
HTML

DECAfpga /MiSTery

Atari ST/STe core demistyfied. See Readme in board folder (Deca, ...)

fpga computers cape cyc1000 demistify 3pins mergefork

UpdatedApr 30, 2022
Assembly

AtlasFPGA /COLOR_PAL_THESONDERS

Incredible code to implementen a pal signal with a level count of pins in verilog.

pal cyc1000 max1000

UpdatedFeb 22, 2023

AtlasFPGA /MULTICORE-ESdUDO-ROJO

microcontroller video composite bluepill kicad usb-host multicore stm32f103c8t6 fpga-board fpga-programming cyc1000

Diseñar la placa - ¡Créalo tu mismo! De coste más reducido para la Fpga CYC1000, con una BLUEPILL STM32F103C8T6

UpdatedDec 11, 2023

AtlasFPGA /DVI_1280x1024_CYC1000

RTL, a graphic form to deal with free wrappers in DVI signals

dvi cyc1000 max1000

UpdatedDec 11, 2023
Verilog

DECAfpga /BBC_DemiSTify

BBC micro - Demistified for Deca & Neptuno. [This fork is only a mirror, not for development]

fpga computers cape cyc1000 demistify 3pins mergefork

UpdatedJul 13, 2022
VHDL

AtlasFPGA /RP2040-PiZero

framework hdmi dvi multicore alma rbf cyc1000 rp2040 rp2040-pizero

UpdatedDec 23, 2023

AtlasFPGA /MODULOS_HARDWARE_MIGUEL_ANGEL_VERILOG

verilog quartus fpga-programming cyc1000

Una muy buena forma de transformar la IO BOARD ATLAS con CYC1000 en una entrenadora en toda regla

UpdatedApr 4, 2023

AtlasFPGA /ALMA_FIRMWARE_AND_CORE_Guillermo_Amat

The core and firmware that uses nowadays the PI-PICO family for use in ATLAS I/O Board is located in GITLAB.

firmware esp cyc1000 max1000 maixbit pi-pico pi-pico-w

UpdatedMay 21, 2023

AtlasFPGA /ZET_PC_HDMI_ATLAS

Error de Fallo de las instancias de memoria en Quartus II Lite dado que son asíncronas.

atlas i8086 cyc1000

UpdatedApr 2, 2023
Verilog

AtlasFPGA /COREFANTASMICO

Core creado por Miguel Angel

verilog hdl cyc1000 max1000

UpdatedApr 4, 2023

AtlasFPGA /Demo_PIOTR.GO_888_DVI

This code creates a bidimensional pattern.

cyc1000 max1000

UpdatedFeb 23, 2023

AtlasFPGA /Practicas_URIEL_TAPIA_MAX1000