combinational-logic
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Nand2Tetris: Build a computer system from the ground up, from nand to tetris. Hardware and software.
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Sep 30, 2017 - Assembly
Materials for the Computer Science course, Digital Design (Logic Circuits)
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Apr 25, 2022 - C++
A 32-bit ALU using combinational logic written in Verilog.
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Oct 18, 2019 - C
An efficient combinatorics library for JavaScript to generate and get the list of all Permutations and Combinations with the ability to enable or disable repetition. (utilizing ES2015 generators)
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Oct 26, 2022 - JavaScript
This is a Combinational Circuit Logic Simulation Tool. There is a C++ version and a C version.
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May 17, 2022 - C++
Design of the implementation of a calculator connected on the integrated FPGA
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Apr 1, 2024 - VHDL
Source code for various Verilog-based projects and assignments
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Nov 8, 2018 - Verilog
Simple Kotlin Project Using Kotlin Language
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Mar 17, 2025 - Kotlin
VHDL projects for combinational and sequential logic design on FPGA.
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Dec 18, 2024 - VHDL
This project implements a 4-bit binary to hexadecimal decoder using basic logic gates, driving a common anode 7-segment display. Designed for simulation in CircuitVerse, it demonstrates practical digital logic design skills for use in embedded systems, control circuits, and digital displays.
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Apr 28, 2025
This repository contains synthesizable VHDL code for basic combinational logic circuits such as Adder with register, 2:4 decoder, 4:2 priority encoder, Multiplier with register and other circuits.
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Dec 19, 2021 - VHDL
MUX VHDL | Układ kombinacyjny VHDL
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Mar 27, 2022 - VHDL
EE89H Final Project
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Dec 24, 2017 - Verilog
Codes written by me in my Digital Logic Design course.
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Jan 23, 2020 - HTML
VHDL implementations of half-adders, full-adders, and a 4-bit adder for digital circuit design
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Oct 18, 2023 - VHDL
simulation of essential combinational logic circuits with boolean algebra
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Mar 27, 2021 - Python
Analyze the combine with and without the repetition. (SOON)
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May 12, 2019 - PHP
This script lists out all paths from inputs to outputs of an input combinational circuit in the form of structural/gate-level modelling in verilog. The BFS graph algorithm is used.
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Nov 4, 2020 - Python
These are the assignments of Second year Analog Digital Electronicd subject
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Oct 31, 2022
CPEN 211: Computing Systems I
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Mar 13, 2025 - SystemVerilog
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