Trace-driven cache memory simulator with LRU, MRU, RR and Belady replacement policies.

• UpdatedDec 22, 2023
• C#

Resources for CSARCH2 (Computer Organization and Architecture 2) to help students prepare for exams and build a strong foundation in computer architecture.

• UpdatedSep 22, 2025

GoCache – High-Performance In-Memory Cache for Go

• UpdatedMay 19, 2025
• Go

"vcache" is a library that provides a concurrent-safe in-memory cache to store key-value pairs.

• UpdatedAug 9, 2023
• Go

Exerting coherency between caches with protocols in a Memory-Shared Multiprocessors system whether it has uniform memory access(UMA, symmetric) or not(non-UMA).

• UpdatedAug 23, 2022
• Verilog

The task is to design a "family" of three microprocessors that differ in performance and cost for the same computational task, as a project in "Computer Architecture 2" course.

• UpdatedJan 15, 2025
• Assembly

This project is an implementation of cache memory with load and store instructions in Verilog.

• UpdatedNov 4, 2017
• C

Global News is designed to provide users with easy access to global news in a seamless and user-friendly manner. The app focuses on delivering a smooth user experience while ensuring that users can easily find and read news articles relevant to their interests and location.

• UpdatedMar 1, 2025
• Dart

Um programa que simula o referenciamento do endereço da memória principal na memória cache.

• UpdatedJan 19, 2022
• C++

RAM and cash memory emulation

• UpdatedAug 23, 2025
• Java

ASP.NET Core (.NET 6) Web API + cache (Redis, Memory)

• UpdatedJul 29, 2022
• C#

A real-time Redis monitoring dashboard with interactive charts and metrics visualization.

• UpdatedJun 16, 2025
• JavaScript

Cache memory management project. Technologies and languages used: C++. University. Computer Structure.

• UpdatedOct 5, 2020
• C

A simulator of cache system behavior.

• UpdatedDec 14, 2021
• C

Codigo python para simular lecturas de un sistema de memoria con RAM y Caché

• UpdatedOct 10, 2024
• Python

Small, lightweight GRPC cache memory service for use in distributed or separate systems with the ability to separate information from each system

• UpdatedMay 9, 2020
• C#

• UpdatedJun 16, 2024
• Ruby

Hands-on exercise for DPE University

• UpdatedMay 17, 2024
• Java

ARM processor implementation, hazard unit, forwarding unit, SRAM & cache memory.

• UpdatedJul 24, 2023
• Verilog

Solution to cachelab of CMU-213

• UpdatedJun 30, 2024
• C