bluespec-systemverilog-language
Here are 5 public repositories matching this topic...
Implementation of Vector Reduce Min and Vector Negation ASIC Hardware, plus a toy CPU, memory and custom ISA for demo. Can be compiled to Verilog. Demos include fib series computations using custom ISA (and custom assembly) and some vector programs.
- Updated
Jan 11, 2021 - Bluespec
CMake modules for building Bluespec targets
- Updated
Aug 6, 2025 - CMake
Bluespec SystemVerilog language definition for the LaTeX listings package
- Updated
Mar 28, 2017 - TeX
Bluespec System Verilog syntax highlighting for Notepad++
- Updated
Jun 27, 2023
A collection of activation functions implemented in Bluespec for integration with hardware designs, ensuring IEEE 754 compliance
- Updated
Dec 11, 2023 - Verilog
Improve this page
Add a description, image, and links to thebluespec-systemverilog-language topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with thebluespec-systemverilog-language topic, visit your repo's landing page and select "manage topics."