一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

• UpdatedSep 15, 2023
• Bluespec

HDL support for VS Code

• UpdatedNov 4, 2025
• TypeScript

Bluespec SystemVerilog extension for VS Code

• UpdatedFeb 6, 2024
• Bluespec

Bluespec System Verilog language extension for Visual Studio Code

• UpdatedMay 11, 2018
• Bluespec

Bluespec SystemVerilog Package for Sublime Text

• UpdatedSep 15, 2015

Forth CPU J1 in Bluespec SystemVerilog (BSV)

• UpdatedApr 30, 2023
• Verilog

Implementation of Vector Reduce Min and Vector Negation ASIC Hardware, plus a toy CPU, memory and custom ISA for demo. Can be compiled to Verilog. Demos include fib series computations using custom ISA (and custom assembly) and some vector programs.

• UpdatedJan 11, 2021
• Bluespec

CMake modules for building Bluespec targets

• UpdatedAug 6, 2025
• CMake

Quark is a single cycle RV32I RISC-V core, The RTL is written in BlueSpec System Verilog (BSV)

• UpdatedJun 9, 2024
• Bluespec

To toy around with Bluespec-SystemVerilog and my Basys3 board

• UpdatedJan 29, 2018
• Bluespec

🐋Docker for Bluespec SystemVerilog (BSV) on WSL2, compatible with WangXuan95/BSV_Tutorial_cn.

• UpdatedJan 8, 2025
• Dockerfile

Aetheron is a minimal RISC-V SoC using a TileLink-lite interconnect and basic peripherals that can run bare metal C programs

• UpdatedJul 18, 2025
• Bluespec

Bluespec implementation of PG routing algorithm on a network on chip running a SMIPS

• UpdatedJul 6, 2017
• Bluespec

Implementação do protocolo TCP para a disciplina de Redes de Computadores da Universidade Federal de São Carlos - UFSCar

• UpdatedNov 5, 2018
• C++

Specula is a Dual-Issue, Out-of-Order RISC-V RV32I core featuring basic Dynamic Scheduling and Register Renaming. Designed for simulation (WIP)

• UpdatedSep 29, 2025
• Bluespec

Bluespec System Verilog syntax highlighting for Notepad++

• UpdatedJun 27, 2023

A collection of activation functions implemented in Bluespec for integration with hardware designs, ensuring IEEE 754 compliance

• UpdatedDec 11, 2023
• Verilog

Wishbone/Bluespec Systemverilog Transactors

• UpdatedFeb 16, 2023
• Verilog

FSM coding styles in BSV

• UpdatedSep 28, 2021
• Verilog

Learning bluespec with bunch of tutorials and example codes

• UpdatedMay 28, 2024
• Bluespec