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ascust /3DMM-Fitting-Pytorch

A 3DMM fitting framework using Pytorch.

pytorch fitting 3d-face face-reconstruction 3dmm 3d-morphable-face-model bfm 3d-face-alignment basel-face-model 3d-morphable-models 3d-face-reconstruction monocular-video-reconstruction

UpdatedJan 12, 2024
Python

TimoBolkart /BFM_to_FLAME

Convert from Basel Face Model (BFM) to the FLAME head model

python computer-vision computer-graphics face-models flame 3d-models bfm basel-face-model face-model flame-model flame-fitting bfm-model flame-mesh

UpdatedFeb 5, 2023
Python

wyvernSemi /pcievhost

PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities

c verification verilog virtual modelling cosim pcie pli bfm

UpdatedOct 31, 2025
C

cutipu /HASOKI

HASOKI DDOS TOOL- powerful DDoS toolkit for penetration tests

http ddos botnet toolkit python-script python3 cloudflare cnc denial-of-service layer7 mutilthread bfm denial httpflood sock5 bypasscloudflare webattack layer7bypass hasoki uambypass

UpdatedDec 16, 2023
Python

nabeel3133 /combining3Dmorphablemodels

Project Page of Combining 3D Morphable Models: A Large scale Face-and-Head Model - [CVPR 2019]

shape pattern matrix regression point gaussian mesh registration pca eigenvectors principal covariance deformation bfm combined nicp morphable corresponding eigenspace lyhm

UpdatedDec 16, 2019
MATLAB

Bemfool /bfm-visual-tool

A Visual Tools of Basel Face Model using Qt5(+built-in OpenGL) and C++

face-reconstruction bfm basel-face-model face-morphable-model

UpdatedFeb 15, 2020
C++

chili-chips-ba /openPCIE

Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes... now for the first time in opensource on the Host side too! Our project roots for Root Port in 4 ways: 1) openRTL; 2) openBFM with unique SIM setup, way faster than vendor's; 3) openSW stack; 4) one-of-a-kind openBackplane.

fpga serdes driver pcb rtl backplane systemverilog rp pcie bfm

UpdatedNov 12, 2025
HTML

nabeel3133 /3D-texture-fitting

Project Page of Synthesizing Normalized Faces From Facial Identity Features - [CVPR 2017]

normalized faces eigenvalues bfm morphable-model texture-fitting ddfa synthesizing texture-eigenspace

UpdatedDec 16, 2019
Python

grigala /3DMMDepthFitting

Efficient 3D Morphable Model Face Fitting using Depth Sensing Technologies

python opencv machine-learning scala computer-vision thesis image-processing bayesian-inference mcmc msc depth-camera 3dmm shape-reconstruction metropolis-hastings bfm basel-face-model 3d-face-modelling 3d-depth-information reconstruction-process probabilistic-fitting

UpdatedApr 19, 2022
Scala

CERC-AAI /bfm

Code for "General-Purpose Brain Foundation Models for Time-Series Neuroimaging Data"

time-series brain brain-computer-interface bfm foundation-models

UpdatedDec 14, 2024
Python

Smorodov /nano_bfm

Basel morphable face model mesh and texture generator using GPU.

cublas face-reconstruction face-morphing bfm face-generation basel-face-model 3d-face-reconstruction morphable-model face-generator face-morphable-model

UpdatedSep 14, 2020
C

ubc-3d-vision-lab /NEO-3DF

face 3d-face bfm 3d-face-alignment 3d-face-reconstruction face-editing

UpdatedDec 9, 2022
Jupyter Notebook

Bemfool /BFM-tools

Tools to use Basel Face Model in C++

opencv face-reconstruction bfm basel-face-model face-morphable-model

UpdatedJun 20, 2021
C++

akaeba /eSpiMasterBfm

Bus functional model of an Enhanced Serial Peripheral Interface (eSPI) master

master vhdl intel testbench vhdl93 bfm vhdl-code espi bus-functional-model enhanced-spi

UpdatedJun 21, 2025
VHDL

midisenpai /spi-bfm

A quick SPI BFM to assist in SPI device testing and development

spi systemverilog fusesoc bfm

UpdatedJan 15, 2024
SystemVerilog

AXI_WB_TB

dg2300 /AXI_WB_TB

Basic UVM Testbench to verify AXI stream spec design. Added a wishbone BFM to mimic Wishbone design.

system-verilog bfm design-verification uvm-verification

UpdatedDec 5, 2023
Verilog

midisenpai /i2c-bfm

A simple I2C BFM

i2c systemverilog fusesoc bfm

UpdatedNov 5, 2022
SystemVerilog

midisenpai /uart-bfm

A simple UART BFM

uart systemverilog fusesoc bfm

UpdatedNov 5, 2022
SystemVerilog

vaseegoo /AXI3_VIP

Xillinx AXI Verification IP VLNV:axi_vip1.1@Vivado 2017.4

UpdatedAug 3, 2018
Verilog

chenjun2hao /3DDFA_V2

the 3DDFA_V2 with 81 face landmarks.

bfm 81landmarks

UpdatedNov 10, 2023
Python

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