32-bit Superscalar RISC-V CPU

• UpdatedSep 18, 2021
• Verilog

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

• UpdatedNov 21, 2020
• C

USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)

• UpdatedJun 6, 2020
• Verilog

Over-engineered SDR development board

• UpdatedNov 23, 2024
• VHDL

Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.

• UpdatedDec 14, 2020
• Verilog

A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.

• UpdatedOct 29, 2023
• VHDL

FPGA Camera Parallel & MIPI Verilog

• UpdatedFeb 21, 2025

HDU Computer Organization Course Design Beginner Guide - 杭电计组课设新手指南

• UpdatedMay 13, 2019
• Verilog

Library to convert a FASM file into BELs importable into Vivado.

• UpdatedSep 25, 2023
• Verilog

My experiments with Nexys4 DDR Artix-7 FPGA Board

• UpdatedOct 1, 2020
• Verilog

Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.

• UpdatedJan 12, 2022
• Verilog

基于蜂鸟E203的魔改

• UpdatedNov 28, 2019
• Verilog

A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)

• UpdatedApr 5, 2022
• VHDL

Created project using a PCIe root-complex and endpoint on a Xilinx Artix-7.

• UpdatedFeb 7, 2023
• VHDL

GRLIB GPL support for Digilent CMOD A7 35T board

• UpdatedJan 5, 2020
• VHDL

A PCB platform based on the architecture of Arm + FPGA

• UpdatedApr 23, 2019
• HTML

Alchitry Au FPGA Board Example Project

• UpdatedJan 12, 2024
• SystemVerilog

This repository contains the Xilinx Vivado project for the Artix-7 (XC7A35T-1FTG256C) FPGA on Virtex.

• UpdatedJul 9, 2022
• SystemVerilog

A simple and scaleable Self Organizing Map implementation written in VHDL. Tested on ARTYA7-35T board.

• UpdatedJan 31, 2021
• VHDL

A tetris-game on screen using verilog.

• UpdatedJan 15, 2020
• Verilog