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#

adder

Here are 160 public repositories matching this topic...

Telegram-Members-Adder

Scrape Telegram group members (hidden members also) and add them to yours.

  • UpdatedAug 3, 2025

Scraper and adder for Telegram supporting multiple accounts at the same time. Adds via Telegram API and only by username. For adding via ID and not needing Telgram API contact me.

  • UpdatedMar 8, 2023
  • Python

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

  • UpdatedJul 17, 2022
  • Verilog

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

  • UpdatedSep 20, 2023
  • Python

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

  • UpdatedOct 2, 2019
  • Verilog
TG-All-In-One-Tool

16-bit Adder Multiplier hardware on Digilent Basys 3

  • UpdatedAug 3, 2023
  • Verilog

Implementing Different Adder Structures in Verilog

  • UpdatedSep 3, 2019
  • Verilog
Telegram-Reporter-Tool

Telegram Group Parser/Scraper and user Adder via id or username with proxy support

  • UpdatedSep 16, 2024
  • Python

Posit Arithmetic Cores generated with FloPoCo

  • UpdatedJun 25, 2024
  • VHDL

Using this tool you can easily add so many members from any group to your group. Less than 2 minutes. Super easy. Time saver. But this tool is only for educational purpose. You could be banned from Telegram. So be careful. Recommanded to use this tool only on Termux.

  • UpdatedJul 11, 2021
  • Python

Instrumenting adders to measure speed

  • UpdatedJun 8, 2022
  • Verilog

Adds members of another group to another group

  • UpdatedSep 9, 2022
  • Python

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