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RISC-V Vector support#2442
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* WIP: initial RVV implementationCo-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>* Fix issue with SIMDJSON_CONDITIONAL_INCLUDE in rvv/implementation.hCo-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>* drop RISC-V V-extension auto-detection in cmake- Remove CMake logic that adds -DSIMDJSON_IS_RVV=1.- Let SIMDJSON_IS_RVV be determined by portability.h.- Translate placeholder comment to English.Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>* fixing amalgamation.Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>* adding baseCo-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>---------Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>Co-authored-by: Daniel Lemire <daniel@lemire.me>
camel-cdr commentedSep 14, 2025
For the RVV backend, I see two options:
I would be more interested in writing (2), but that will take some time. I think it's best to do both, then we can compare which is faster and, if (1) is faster, we can still use (2) as a fallback for longer vectors. |
…or RVV Optimization (#2455)* implement rvv/intrinsics.h for dynamic vector lengthCo-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>* Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guardCo-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>* Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guardCo-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>---------Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
camel-cdr commentedSep 18, 2025
You can't put dynamic code into |
SaberAlterr commentedSep 19, 2025
@camel-cdr |
…der (#2469)* Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guardCo-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>* Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guardCo-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>* Fix intrinsics header and add 128-bit SIMD layerCo-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>---------Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
camel-cdr commentedSep 24, 2025 • edited
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This fails to build, because you can't put RVV types into structs, since they are sizeless-types. Ideally the fixed width backend would be compiled for You should really compile and run the code locally before sending a PR. |
* Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guardCo-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>* Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guardCo-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>* Implement simd8/simd8x64 with RVV intrinsics and fallback bitmanipulationCo-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>* Fix missing SIMDJSON_CONDITIONAL_INCLUDE guardCo-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>* Fix missing SIMDJSON_CONDITIONAL_INCLUDE guardCo-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>---------Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
This draft pull request serves to indicate progress towards RISC-V support.
The foundation has been done by@SaberAlterr but we need to actual RISC-V specific optimizations.
cc@camel-cdr
See#2423