Commitf67d061

danicampora

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cc3200: Fix SPI clock divider calculation.

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Lines changed: 3 additions & 9 deletions

Original file line number	Diff line number	Diff line change
`@@ -782,23 +782,17 @@ SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk,`
`782`	`782`	`}`
`783`	`783`
`784`	`784`	`//`
`785`		`-// Mask the configurations and set clock divider granularity`
`786`		`-// to 1 cycle`
	`785`	`+// set clock divider granularity to 1 cycle`
`787`	`786`	`//`
`788`		`-ulRegData= (ulRegData& (~(MCSPI_CH0CONF_WL_M \|`
`789`		`-MCSPI_CH0CONF_EPOL \|`
`790`		`-MCSPI_CH0CONF_POL \|`
`791`		`-MCSPI_CH0CONF_PHA \|`
`792`		`-MCSPI_CH0CONF_TURBO ) \|`
`793`		`-MCSPI_CH0CONF_CLKG));`
	`787`	`+ulRegData \|=MCSPI_CH0CONF_CLKG;`
`794`	`788`
`795`	`789`	`//`
`796`	`790`	`// Get the divider value`
`797`	`791`	`//`
`798`	`792`	`ulDivider= ((ulSPIClk/ulBitRate)-1);`
`799`	`793`
`800`	`794`	`//`
`801`		`-// The least significant four bits of the divider is usedfo configure`
	`795`	`+// The least significant four bits of the divider is usedto configure`
`802`	`796`	`// CLKD in MCSPI_CHCONF next eight least significant bits are used to`
`803`	`797`	`// configure the EXTCLK in MCSPI_CHCTRL`
`804`	`798`	`//`

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