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Complete Integrated Circuit (IC) Layout Analysis from GDSII Design File to Parasitics Extraction

This layout analyzer is written in C++ as part of a wider API for the electromagnetic design validation of VLSI IC, package, and board designs. The code design follows a philosophy intended to have the most extensibility and highest level of automation possible for increasingly complex integrated circuits, packages, and boards. Design information from the Graphic Database Stream II (GDSII) file is parsed and stored alongside simulation input information.

A nonstandard mode of operation allows an interconnect modeling platform (IMP) file to be translated to a GDSII file design. Another nonstandard control mode translates a GDSII file design into aPlanar Straight Line Graph which may be used as input to Delaunay triangulation software.

Once a design is loaded, the information can be written to another GDSII file or analyzed with a full-wave simulation to extract parasitics between user-specified ports. Parasitics are preferably reported through aXyce subcircuit file (SPICE derivative from Sandia National Laboratories), though aStandard Parasitic Exchange Format (SPEF) file may be output alternatively. Please carefully read thisREADME.md file for an overview, dependencies, and usage instructions.

Note that modern compilers that support the following language standards are needed to make the package dependencies: GNU Fortran (superset of F95) for Fortran, C99 for C language, and C++17 for C++.

All software is under active development without any notices regarding the timing of nature of updates. Contributions are welcome through forking andpull requests. Please direct all questions, bug reports, and issues relating to this repository to the primary maintainer:

• Dan Jiao, Synopsys Professor of ECE, Elmore Family School of ECE, Purdue University

Developers:

• Michael Hayashi, Former Graduate Research Assistant, Elmore Family School of ECE, Purdue University
• Dr. Li Xue, Former Graduate Research Assistant, Elmore Family School of ECE, Purdue University
• Dr. Shuzhan Sun, Former Graduate Research Assistant, Elmore Family School of ECE, Purdue University

Many thanks are owed to the project sponsors for making the development of this software possible:

Follow the instructions given inINSTALL.md to install this software and run it from the command line. Users from Purdue University should readpurdue_install.md instead for specific steps unique to their environment.

Every GDSII file needs to have a simulation input file with the .sim_input extension created for it. The custom syntax of the simulation input file is given at the bottom of this section. It is important that the information in the blocks underneath the headers in all capital letters appear in the order given. Comments start with '#' and continue for the rest of the line. Comments may appear almost anywhere in the file so long as in-line comments are preceded by a space. The following are placeholders, angle brackets and words in between, which must populated depending on the design:

• <six design extents>: The six coordinates for the smallest rectangular prism enclosing the design with implied units in the order of xmin (the smallest x-coordinate in the design), xmax, ymin, ymax, zmin, and zmax (the largest z-coordinate in the design).
  • A lowercase 'e' may be used for scientific notation.
  • For example,30.00 +149. -47.0 +120. 0.00 +7.53.
• <lengthUnit>: The unit by which all given and reported lengths (e.g., total size of design, layer coordinates and heights, and port coordinates) must be multiplied in order to convert to meters. A lowercase 'e' may be used for scientific notation. For example,1e-6.
• <freqUnit>: The unit by which all given and reported temporal frequencies must be multiplied in order to convert to hertz. A lowercase 'e' may be used for scientific notation. For example,1.0e+6.
• <freqStart>: The smallest frequency in the frequency sweep with implied units. For example,1000.0.
• <freqEnd>: The largest frequency in the frequency sweep with implied units. For example,3000.0.
• <nfreq>: The total number of frequencies to include in the sweep. A value of1 means that <freqEnd> must equal <freqStart>. A value of2 means that only <freqStart> and <freqEnd> are included. Any larger integer requires interpolation.
• <freqScale>: Integer representing the scale for frequency interpolation. The recommended value is0 for logarithmic spacing. The value1 is for linear spacing.
• <numLayer>: The total number of layers in this design. The integer here must match the number of active <layer entry> lines following this line in the file.
• <layer entry>: An entire line representing a single layer.
  • The four pieces of information that must be included in order are the layer name at the start of the line, the z-coordinate of the bottom of the layer (designated with 'z = ' before a length with implied units), the height of the layer (designated with 'h = ' before a length with implied units), and the relative permittivity of the dielectric making up that insulating parts of that layer (designated with 'e = ' before a unitless floating-point number greater than or equal to unity).
  • A lowercase 'e' may be used for scientific notation.
  • In order to maintain correspondence with the layer numbers used in a GDSII file, the layer names must be a plain integer (recommended) or be an alphanumeric string with a capital 'M' before the layer number.
  • Optional specifications for each layer entry include the conductivity of conductors in that layer (designated with 'sigma = ' before a nonnegative floating-point number with units of S/m) and the dielectric loss tangent (designated with 'TanD = ' before a nonnegative, unitless floating-point number).
  • It is recommended to add one layer below the bottommost GDSII layer and a second layer above the topmost GDSII layer to serve as planes of perfect electrical conductor (PEC) representing how the design would behave in a testing environment.
  • For example,ILDM2 z = 1.316 h = 0.12 e = 8.0.
• <numPorts>: The total number of ports in this design. The integer here must match the number of active <port entry> lines following this line in the file.
• <port entry>: An entire line representing a single port excitation.
  • The eight pieces of information that must be included in order are the port name, the x-coordinate of the supply point of the port, the y-coordinate of the supply point of the port, the z-coordinate of the supply point of the port, the x-coordinate of the return point of the port, the y-coordinate of the return point of the port, the z-coordinate of the return point of the port, and the directionality of the port.
  • Port entries sharing the same name will be converted to a single port with multiple excitations.
  • A lowercase 'e' may be used for scientific notation.
  • The directionality of the port is either '+1' for input ports, '-1' for output ports, or '0' for bidirectional ports or ports with uncertain power flow.
  • A port should be added for each input/output pin of the device. Additional ports are needed for every transistor or other active device in the design. For printed circuit boards (PCBs), at least one port is needed for each component on the populated layout.
  • For example,port1 +146. -16.0 4.53 +146. +6.00 4.53 -1.

TOTAL SIZE<six design extents>lengthUnit = <lengthUnit>FREQUENCYfreqUnit = <freqUnit>freqStart = <freqStart>freqEnd = <freqEnd># Block-interrupting commentnfreq = <nfreq>freqScale = <freqScale>DIELECTRIC STACKnumStack = <numLayer><layer entry> # In-line comment<...><layer entry> # In-line comment# Post-block commentPORTnumPorts = <numPorts><port entry> # In-line comment<...><port entry> # In-line comment# Post-block comment

• Example Files
  • Purdue On-Chip Electromagnetics Laboratory forsingleStrip.imp (single stripline)
  • Yuan Ze University Design Automation library forinv.gds (inverter logic gate),nand2.gds (2-input NAND gate), andxor.gds (XOR gate)
  • NanGate Open Cell Library FreePDK45 forSDFFRS_X2.gds (scan D flip-flop with reset/set)
  • Peter Monta and theTuva Design Intel 4004 Anniversary Project for4004.gds (Intel 4004 processor from 1971)
  • Open Compute Project for original Gerber files for Facebook Wedge 100 that led toWEDGE100_REV01.gds (100G Ethernet Switch board)
• Prof. Dan Jiao of the Purdue On-Chip Electromagnetics Laboratory for her guidance of the project
• The staff of the Defense Advanced Research Projects Agency (DARPA) Microsystems Technology Office (MTO) for their sponsorship, feedback, and support of this endeavor
• Prof. C.J. Richard Shi and the students of theUniversity of Washington RAIL research group forsupplying designs and validating solver results against commercial tools
• The other contributors of theIntelligent Design of Electronic Assets (IDEA) team and thePosh Open Source Hardware (POSH) team within the DARPA Electronics Resurgence Initiative (ERI)

GNU Public License v2.0 (seeLICENSE)