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1. DeeployDeeployPublic

   DNN Compiler for Heterogeneous SoCs

   Python 53 25

2. carfieldcarfieldPublic

   A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

   Tcl 114 25

3. cheshirecheshirePublic

   A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

   Verilog 295 83

4. snitch_clustersnitch_clusterPublic

   An energy-efficient RISC-V floating-point compute cluster.

   C 113 89

5. axiaxiPublic

   AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

   SystemVerilog 1.4k 317

6. araaraPublic

   The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

   C 469 165