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Commitc5d34f4

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Fix generic read and write barriers for Clang.
generic-gcc.h maps our read and write barriers to C11 acquire andrelease fences using compiler builtins, for platforms where we don'thave our own hand-rolled assembler. This is apparently enough for GCC,but the C11 memory model is only defined in terms of atomic accesses,and our barriers for non-atomic, non-volatile accesses were not alwaysrespected under Clang's stricter interpretation of the standard.This explains the occasional breakage observed on new RISC-V + Clanganimal greenfly in lock-free PgAioHandle manipulation code containing arepeating pattern of loads and read barriers. The problem can also beobserved in code generated for MIPS and LoongAarch, though we aren'tcurrently testing those with Clang, and on x86, though we use our ownassembler there. The scariest aspect is that we use the generic versionon very common ARM systems, but it doesn't seem to reorder the relevantcode there (or we'd have debugged this long ago).Fix by inserting an explicit compiler barrier. It expands to an emptyassembler block declared to have memory side-effects, so registers areflushed and reordering is prevented. In those respects this is like thearchitecture-specific assembler versions, but the compiler is still incharge of generating the appropriate fence instruction. Done for writebarriers on principle, though concrete problems have only been observedwith read barriers.Reported-by: Alexander Lakhin <exclusion@gmail.com>Tested-by: Alexander Lakhin <exclusion@gmail.com>Discussion:https://postgr.es/m/d79691be-22bd-457d-9d90-18033b78c40a%40gmail.comBackpatch-through: 13
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‎src/include/port/atomics/generic-gcc.h‎

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Original file line numberDiff line numberDiff line change
@@ -44,12 +44,20 @@
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#if !defined(pg_read_barrier_impl)&& defined(HAVE_GCC__ATOMIC_INT32_CAS)
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/* acquire semantics include read barrier semantics */
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#definepg_read_barrier_impl()__atomic_thread_fence(__ATOMIC_ACQUIRE)
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#definepg_read_barrier_impl() do \
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{ \
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pg_compiler_barrier_impl(); \
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__atomic_thread_fence(__ATOMIC_ACQUIRE); \
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} while (0)
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#endif
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#if !defined(pg_write_barrier_impl)&& defined(HAVE_GCC__ATOMIC_INT32_CAS)
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/* release semantics include write barrier semantics */
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#definepg_write_barrier_impl()__atomic_thread_fence(__ATOMIC_RELEASE)
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#definepg_write_barrier_impl() do \
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{ \
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pg_compiler_barrier_impl(); \
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__atomic_thread_fence(__ATOMIC_RELEASE); \
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} while (0)
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#endif
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