Hardware and Computer Systems Engineer
- University of Ioannina
- Ioannina, Greece
- @pantelisEVs
- in/patsaoglou-pantelis
Highlights
- Pro
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- LRS-NODE-1
LRS-NODE-1 PublicIoT node based on a LoraWAN STM32WLE module used for Environmental Monitoring (Hackathon 2025 follow-up)
- JTAG-IEEE-1149.1
JTAG-IEEE-1149.1 PublicBasic JTAG standard implementation in Verilog and integration with a CUT
Verilog 3
- MYS-6ULX-IOT-spidev-dts
MYS-6ULX-IOT-spidev-dts PublicModified device tree for the MYS-6ULX-IOT dev board based on the IMX6ULL to enable SPIDEV
- oosCompiler
oosCompiler PublicAn Object Oriented programming language made using the ANTLR Framework to produce a final C source file that gets compiled into binary using GCC
Python 4
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