Repository files navigation

yosys -- Yosys Open SYnthesis SuiteCopyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>Permission to use, copy, modify, and/or distribute this software for anypurpose with or without fee is hereby granted, provided that the abovecopyright notice and this permission notice appear in all copies.THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIESWITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OFMERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FORANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGESWHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN ANACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OFOR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

This is a framework for RTL synthesis tools. It currently hasextensive Verilog-2005 support and provides a basic set ofsynthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combiningthe existing passes (algorithms) using synthesis scripts andadding additional passes as needed by extending the yosys C++code base.

Yosys is free software licensed under the ISC license (a GPLcompatible license that is similar in terms to the MIT licenseor the 2-clause BSD license).

More information and documentation can be found on the Yosys web site:

• https://yosyshq.net/yosys/

The "Documentation" page on the web site contains links to more resources,including a manual that even describes some of the Yosys internals:

• https://yosyshq.net/yosys/documentation.html

The directoryguidelines contains additional informationfor people interested in using the Yosys C++ APIs.

Users interested in formal verification might want to use the formal verificationfront-end for Yosys, SymbiYosys:

• https://symbiyosys.readthedocs.io/en/latest/
• https://github.com/YosysHQ/SymbiYosys

Yosys is part of theTabby CAD Suite and theOSS CAD Suite! The easiest way to use yosys is to install the binary software suite, which contains all required dependencies and related tools.

• Contact YosysHQ for aTabby CAD Suite Evaluation License and download link
• OR go tohttps://github.com/YosysHQ/oss-cad-suite-build/releases to download the free OSS CAD Suite
• Follow theInstall Instructions on GitHub

Make sure to get a Tabby CAD Suite Evaluation License if you need features such as industry-grade SystemVerilog and VHDL parsers!

For more information about the difference between Tabby CAD Suite and the OSS CAD Suite, please visithttps://www.yosyshq.com/tabby-cad-datasheet

Many Linux distributions also provide Yosys binaries, some more up to date than others. Check with your package manager!

You need a C++ compiler with C++11 support (up-to-date CLANG or GCC isrecommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.TCL, readline and libffi are optional (seeENABLE_* settings in Makefile).Xdot (graphviz) is used by theshow command in yosys to display schematics.

For example on Ubuntu Linux 16.04 LTS the following commands will install allprerequisites for building yosys:

$ sudo apt-get install build-essential clang bison flex \libreadline-dev gawk tcl-dev libffi-dev git \graphviz xdot pkg-config python3 libboost-system-dev \libboost-python-dev libboost-filesystem-dev zlib1g-dev

Similarily, on Mac OS X Homebrew can be used to install dependencies (from within cloned yosys repository):

$ brew tap Homebrew/bundle && brew bundle

or MacPorts:

$ sudo port install bison flex readline gawk libffi \git graphviz pkgconfig python36 boost zlib tcl

On FreeBSD use the following command to install all prerequisites:

# pkg install bison flex readline gawk libffi\git graphviz pkgconf python3 python36 tcl-wrapper boost-libs

On FreeBSD system use gmake instead of make. To run tests use:% MAKE=gmake CC=cc gmake test

For Cygwin use the following command to install all prerequisites, or select these additional packages:

setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build,zlib-devel

The environment variableCXX can be used to control the C++ compiler used, orrun one of the following:

$ make config-clang$ make config-gcc

Note that these will result inmake ignoring theCXX environment variable,unlessCXX is assigned in the call to make, e.g.

$ make CXX=$CXX

For other compilers and build configurations it might benecessary to make some changes to the config section of theMakefile.

$ vi Makefile            # ..or..$ vi Makefile.conf

To build Yosys simply type 'make' in this directory.

$ make$ sudo make install

Note that this also downloads, builds and installs ABC (using yosys-abcas executable name).

Tests are located in the tests subdirectory and can be executed using the test target. Note that you need gawk as well as a recent version of iverilog (i.e. build from git). Then, execute tests via:

$ make test

To use a separate (out-of-tree) build directory, provide a path to the Makefile.

$ mkdir build; cd build$ make -f ../Makefile

Out-of-tree builds require a clean source tree.

Yosys can be used with the interactive command shell, withsynthesis scripts or with command line arguments. Let's performa simple synthesis job using the interactive command shell:

$ ./yosysyosys>

the commandhelp can be used to print a list of all availablecommands andhelp <command> to print details on the specified command:

yosys> help help

reading and elaborating the design using the Verilog frontend:

yosys> read -sv tests/simple/fiedler-cooley.vyosys> hierarchy -top up3down5

writing the design to the console in the RTLIL format used by Yosysinternally:

yosys> write_rtlil

convert processes (always blocks) to netlist elements and performsome simple optimizations:

yosys> proc; opt

display design netlist usingxdot:

yosys> show

the same thing usinggv as postscript viewer:

yosys> show -format ps -viewer gv

translating netlist to gate logic and perform some simple optimizations:

yosys> techmap; opt

write design netlist to a new Verilog file:

yosys> write_verilog synth.v

or using a simple synthesis script:

$ cat synth.ysread -sv tests/simple/fiedler-cooley.vhierarchy -top up3down5proc; opt; techmap; optwrite_verilog synth.v$ ./yosys synth.ys

If ABC is enabled in the Yosys build configuration and a cell library is givenin the liberty filemycells.lib, the following synthesis script willsynthesize for the given cell library:

# read designread -sv tests/simple/fiedler-cooley.vhierarchy -top up3down5# the high-level stuffproc; fsm; opt; memory; opt# mapping to internal cell librarytechmap; opt# mapping flip-flops to mycells.libdfflibmap -liberty mycells.lib# mapping logic to mycells.libabc -liberty mycells.lib# cleanupclean

If you do not have a liberty file but want to test this synthesis script,you can use the fileexamples/cmos/cmos_cells.lib from the yosys sourcesas simple example.

Liberty file downloads for and information about free and open ASIC standardcell libraries can be found here:

• http://www.vlsitechnology.org/html/libraries.html
• http://www.vlsitechnology.org/synopsys/vsclib013.lib

The commandsynth provides a good default synthesis script (seehelp synth):

read -sv tests/simple/fiedler-cooley.vsynth -top up3down5# mapping to target cellsdfflibmap -liberty mycells.libabc -liberty mycells.libclean

The commandprep provides a good default word-level synthesis script, asused in SMT-based formal verification.

The following Verilog-2005 features are not supported byYosys and there are currently no plans to add supportfor them:

• Non-synthesizable language features as defined inIEC 62142(E):2005 / IEEE Std. 1364.1(E):2002

• Thetri,triand andtrior net types

• Theconfig anddisable keywords and library map files

• Thefull_case attribute on case statements is supported(also the non-standard// synopsys full_case directive)

• Theparallel_case attribute on case statements is supported(also the non-standard// synopsys parallel_case directive)

• The// synopsys translate_off and// synopsys translate_ondirectives are also supported (but the use of`ifdef .. `endifis strongly recommended instead).

• Thenomem2reg attribute on modules or arrays prohibits theautomatic early conversion of arrays to separate registers. Thisis potentially dangerous. Usually the front-end has good reasonsfor converting an array to a list of registers. Prohibiting thisstep will likely result in incorrect synthesis results.

• Themem2reg attribute on modules or arrays forces the earlyconversion of arrays to separate registers.

• Thenomeminit attribute on modules or arrays prohibits thecreation of initialized memories. This effectively putsmem2regon all memories that are written to in aninitial block andare not ROMs.

• Thenolatches attribute on modules or always-blocksprohibits the generation of logic-loops for latches. Insteadall not explicitly assigned values default to x-bits. This doesnot affect clocked storage elements such as flip-flops.

• Thenosync attribute on registers prohibits the generation of astorage element. The register itself will always have all bits setto 'x' (undefined). The variable may only be used as blocking assignedtemporary variable within an always block. This is mostly used internallyby Yosys to synthesize Verilog functions and access arrays.

• Thenowrshmsk attribute on a register prohibits the generation ofshift-and-mask type circuits for writing to bit slices of that register.

• Theonehot attribute on wires mark them as one-hot state register. Thisis used for example for memory port sharing and set by the fsm_map pass.

• Theblackbox attribute on modules is used to mark empty stub modulesthat have the same ports as the real thing but do not contain informationon the internal configuration. This modules are only used by the synthesispasses to identify input and output ports of cells. The Verilog backendalso does not output blackbox modules on default.read_verilog, unlesscalled with-noblackbox will automatically set the blackbox attributeon any empty module it reads.

• Thenoblackbox attribute set on an empty module preventsread_verilogfrom automatically setting the blackbox attribute on the module.

• Thewhitebox attribute on modules triggers the same behavior asblackbox, but is for whitebox modules, i.e. library modules thatcontain a behavioral model of the cell type.

• Thelib_whitebox attribute overwriteswhitebox whenread_verilogis run in-lib mode. Otherwise it's automatically removed.

• Thedynports attribute is used by the Verilog front-end to mark modulesthat have ports with a width that depends on a parameter.

• Thehdlname attribute is used by some passes to document the original(HDL) name of a module when renaming a module. It should contain a singlename, or, when describing a hierarchical name in a flattened design, multiplenames separated by a single space character.

• Thekeep attribute on cells and wires is used to mark objects that shouldnever be removed by the optimizer. This is used for example for cells thathave hidden connections that are not part of the netlist, such as IO pads.Setting thekeep attribute on a module has the same effect as setting iton all instances of the module.

• Thekeep_hierarchy attribute on cells and modules keeps theflattencommand from flattening the indicated cells and modules.

• Theinit attribute on wires is set by the frontend when a register isinitialized "FPGA-style" withreg foo = val. It can be used duringsynthesis to add the necessary reset logic.

• Thetop attribute on a module marks this module as the top of thedesign hierarchy. Thehierarchy command sets this attribute when calledwith-top. Other commands, such asflatten and various backendsuse this attribute to determine the top module.

• Thesrc attribute is set on cells and wires created by to the string<hdl-file-name>:<line-number> by the HDL front-end and is then carriedthrough the synthesis. When entities are combined, a new |-separatedstring is created that contains all the string from the original entities.

• Thedefaultvalue attribute is used to store default values formodule inputs. The attribute is attached to the input wire by the HDLfront-end when the input is declared with a default value.

• Theparameter andlocalparam attributes are used to mark wiresthat represent module parameters or localparams (when the HDL front-endis run in-pwires mode).

• Wires marked with thehierconn attribute are connected to wires with thesame name (formatcell_name.identifier) when they are imported fromsub-modules byflatten.

• Theclkbuf_driver attribute can be set on an output port of a blackboxmodule to mark it as a clock buffer output, and thus preventclkbufmapfrom inserting another clock buffer on a net driven by such output.

• Theclkbuf_sink attribute can be set on an input port of a module torequest clock buffer insertion by theclkbufmap pass.

• Theclkbuf_inv attribute can be set on an output port of a modulewith the value set to the name of an input port of that module. Whentheclkbufmap would otherwise insert a clock buffer on this output,it will instead try inserting the clock buffer on the input port (thisis used to implement clock inverter cells that clock buffer insertionwill "see through").

• Theclkbuf_inhibit is the default attribute to set on a wire to preventautomatic clock buffer insertion byclkbufmap. This behaviour can beoverridden by providing a custom selection toclkbufmap.

• Theinvertible_pin attribute can be set on a port to mark it asinvertible via a cell parameter. The name of the inversion parameteris specified as the value of this attribute. The value of the inversionparameter must be of the same width as the port, with 1 indicatingan inverted bit and 0 indicating a non-inverted bit.

• Theiopad_external_pin attribute on a blackbox module's port marksit as the external-facing pin of an I/O pad, and preventsiopadmapfrom inserting another pad cell on it.

• The module attributeabc9_lut is an integer attribute indicating toabc9 that this module describes a LUT with an area cost of this value, andpropagation delays described usingspecify statements.

• The module attributeabc9_box is a boolean specifying a black/white-boxdefinition, with propagation delays described usingspecify statements, foruse byabc9.

• The port attributeabc9_carry marks the carry-in (if an input port) andcarry-out (if output port) ports of a box. This information is necessary forabc9 to preserve the integrity of carry-chains. Specifying this attributeonto a bus port will affect only its most significant bit.

• The module attributeabc9_flop is a boolean marking the module as aflip-flop. This allowsabc9 to analyse its contents in order to performsequential synthesis.

• The frontend sets attributesalways_comb,always_latch andalways_ff on processes derived from SystemVerilog style always blocksaccording to the type of the always. These are checked for correctness inproc_dlatch.

• The cell attributewildcard_port_conns represents wildcard portconnections (SystemVerilog.*). These are resolved to concreteconnections to matching wires inhierarchy.

• In addition to the(* ... *) attribute syntax, Yosys supportsthe non-standard{* ... *} attribute syntax to set default attributesfor everything that comes after the{* ... *} statement. (Resetby adding an empty{* *} statement.)

• In module parameter and port declarations, and cell port and parameterlists, a trailing comma is ignored. This simplifies writing Verilog codegenerators a bit in some cases.

• Modules can be declared withmodule mod_name(...); (with three dotsinstead of a list of module ports). With this syntax it is sufficientto simply declare a module port as 'input' or 'output' in the modulebody.

• When defining a macro with `define, all text between triple double quotesis interpreted as macro body, even if it contains unescaped newlines. Thetriple double quotes are removed from the macro body. For example:

  `define MY_MACRO(a, b) """   assign a = 23;   assign b = 42;"""

• The attributevia_celltype can be used to implement a Verilog task orfunction by instantiating the specified cell type. The value is the nameof the cell type to use. For functions the name of the output port canbe specified by appending it to the cell type separated by a whitespace.The body of the task or function is unused in this case and can be usedto specify a behavioral model of the cell type for simulation. For example:

  module my_add3(A, B, C, Y);  parameter WIDTH = 8;  input [WIDTH-1:0] A, B, C;  output [WIDTH-1:0] Y;  ...endmodulemodule top;  ...  (* via_celltype = "my_add3 Y" *)  (* via_celltype_defparam_WIDTH = 32 *)  function [31:0] add3;    input [31:0] A, B, C;    begin      add3 = A + B + C;    end  endfunction  ...endmodule

• Thewiretype attribute is added by the verilog parser for wires of atypedef'd type to indicate the type identifier.

• Variousenum_value_{value} attributes are added to wires of an enumerated typeto give a map of possible enum items to their values.

• Theenum_base_type attribute is added to enum items to indicate whichenum they belong to (enums -- anonymous and otherwise -- areautomatically named with an auto-incrementing counter). Note that enumsare currently not strongly typed.

• A limited subset of DPI-C functions is supported. The plugin mechanism(seehelp plugin) can be used to load .so files with implementationsof DPI-C routines. As a non-standard extension it is possible to specifya plugin alias using the<alias>: syntax. For example:

  module dpitest;  import "DPI-C" function foo:round = real my_round (real);  parameter real r = my_round(12.345);endmodule$ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'

• Sized constants (the syntax<size>'s?[bodh]<value>) support constantexpressions as<size>. If the expression is not a simple identifier, itmust be put in parentheses. Examples:WIDTH'd42,(4+2)'b101010

• The system tasks$finish,$stop and$display are supported ininitial blocks in an unconditional context (only if/case statements onexpressions over parameters and constant values are allowed). The intendeduse for this is synthesis-time DRC.

• There is limited support for convertingspecify ..endspecifystatements to special$specify2,$specify3, and$specrule cells,for use in blackboxes and whiteboxes. Useread_verilog -specify toenable this functionality. (By default these blocks are ignored.)

• Thereprocess_after internal attribute is used by the Verilog frontend tomark cells with bindings which might depend on the specified instantiatedmodule. Modules with such cells will be reprocessed during thehierarchypass once the referenced module definition(s) become available.

• Thesmtlib2_module attribute can be set on a blackbox module to specify aformal model directly using SMT-LIB 2. For such a module, thesmtlib2_comb_expr attribute can be used on output ports to define theirvalue using an SMT-LIB 2 expression. For example:

  (* blackbox *)(* smtlib2_module *)module submod(a, b);  input [7:0] a;  (* smtlib2_comb_expr = "(bvnot a)" *)  output [7:0] b;endmodule

• Support forassert,assume,restrict, andcover is enabledwhenread_verilog is called with-formal.

• The system task$initstate evaluates to 1 in the initial state andto 0 otherwise.

• The system function$anyconst evaluates to any constant value. This isequivalent to declaring a reg asrand const, but also works outsideof checkers. (Yosys also supportsrand const outside checkers.)

• The system function$anyseq evaluates to any value, possibly a differentvalue in each cycle. This is equivalent to declaring a reg asrand,but also works outside of checkers. (Yosys also supportsrandvariables outside checkers.)

• The system functions$allconst and$allseq can be used to constructformal exist-forall problems. Assumptions only hold if the trace satisfiesthe assumption for all$allconst/$allseq values. For assertions and coverstatements it is sufficient if just one$allconst/$allseq value triggersthe property (similar to$anyconst/$anyseq).

• Wires/registers declared using theanyconst/anyseq/allconst/allseq attribute(for example(* anyconst *) reg [7:0] foobar;) will behave as if drivenby a$anyconst/$anyseq/$allconst/$allseq function.

• The SystemVerilog tasks$past,$stable,$rose and$fell aresupported in any clocked block.

• The syntax@($global_clock) can be used to create FFs that have noexplicit clock input ($ff cells). The same can be achieved by using@(posedge <netname>) or@(negedge <netname>) when<netname>is marked with the(* gclk *) Verilog attribute.

Whenread_verilog is called with-sv, it accepts some language featuresfrom SystemVerilog:

• Theassert statement from SystemVerilog is supported in its most basicform. In module context:assert property (<expression>); and within analways block:assert(<expression>);. It is transformed to an$assert cell.

• Theassume,restrict, andcover statements from SystemVerilog arealso supported. The same limitations as with theassert statement apply.

• The keywordsalways_comb,always_ff andalways_latch,logicandbit are supported.

• Declaring free variables withrand andrand const is supported.

• Checkers without a port list that do not need to be instantiated (but insteadbehave like a named block) are supported.

• SystemVerilog packages are supported. Once a SystemVerilog file is readinto a design withread_verilog, all its packages are available toSystemVerilog files being read into the same design afterwards.

• typedefs are supported (including inside packages)

  • type casts are currently not supported

• enums are supported (including inside packages)

  • but are currently not strongly typed

• packed structs and unions are supported

  • arrays of packed structs/unions are currently not supported
  • structure literals are currently not supported

• multidimensional arrays are supported

  • array assignment of unpacked arrays is currently not supported
  • array literals are currently not supported

• SystemVerilog interfaces (SVIs) are supported. Modports for specifying whetherports are inputs or outputs are supported.

• Assignments within expressions are supported.

Note that there is no need to build the manual if you just want to read it.Simply visithttps://yosys.readthedocs.io/en/latest/ instead.

In addition to those packages listed above for building Yosys from source, thefollowing are used for building the website:

$ sudo apt install pdf2svg faketime

PDFLaTeX, included with most LaTeX distributions, is also needed during thebuild process for the website. Or, run the following:

$ sudo apt install texlive-latex-base texlive-latex-extra latexmk

The Python package, Sphinx, is needed along with those listed indocs/source/requirements.txt:

$ pip install -U sphinx -r docs/source/requirements.txt

From the root of the repository, runmake docs. This will build/rebuild yosysas necessary before generating the website documentation from the yosys helpcommands. To build for pdf instead of html, callmake docs DOC_TARGET=latexpdf.