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-> [Projects ]
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Here, I will try to organize a study roadmap for people interested in Analog & Mixed-Signal design, based on what I found useful during my studies:

1. Analog Design Basics
2. Digital Circuits Basics
3. PLLs (Phase-Locked Loops)
4. ADCs (Analog/Digital Converters)
5. LDOs (Low-Dropout Regulators)
6. RF receiver system
7. IO/SERDES system
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• Layout
• Cadence Tutorials
• Razavi References
• Razavi AnalogMind Articles -drive
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• Interview Questions
• Resume-Building Docs

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1. Analog-Design-of-Asynchronous-SAR-ADCAnalog-Design-of-Asynchronous-SAR-ADCPublic

   This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.

   152 19

2. Analog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmpAnalog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmpPublic

   This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.

   30 9

3. FPGA-Design-of-a-Digital-Analog-Clock-Display-using-Digilent-Basys3-Artix-7FPGA-Design-of-a-Digital-Analog-Clock-Display-using-Digilent-Basys3-Artix-7Public

   The project uses a Xilinx Artix-7 FPGA on a Digilent Basys 3 board to design a clock whose seconds, minutes, & hours are displayed on a Quad 7-segment display & can also be displayed on a vga displ…

   VHDL 19 11

4. Layout-Design-of-an-8x8-SRAM-arrayLayout-Design-of-an-8x8-SRAM-arrayPublic

   The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static N…

   MATLAB 70 9

5. Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DACModeling-of-10-bit-Pipeline-ADC-and-10-bit-DACPublic

   This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pi…

   MATLAB 25 12

6. RF-design-of-1.9-GHz-Rx-frontendRF-design-of-1.9-GHz-Rx-frontendPublic

   This project shows the design process of the main blocks of a typical RX frontend system.

   23 3