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Politecnico di Milano 2020

The project consists in developing a hardware component in VHDL implementing the Working Zone encoding of the provided addresses. The component interfaces with a memory from which it reads input data and where it writes the result of the conversion.

The documentation for the project is available on GitHub Pages atmrweiss0.github.io/project-reti-logiche-2020

Print to PDF withPrince

prince --javascript --no-artificial-fonts index.html

Or print in browser, but with less features (no page numbers).

Tests are implemented intest_p.vhd intest sourceswith three procedures common for every testbench.

The data for each test are in a separated filegenerated running the scripttest.pywith the configuration intest.ini.Each section in the configuration generates a test with the given parameters,values can be manually inserted or randomly generated.
Configuration parameters are explained intest.py.

Generate test data

python3 generate.py

Get vivado-git submodule

git submodule initgit submodule update

Regenerate project with vivado-git

python2 vivado-git/checkout.py

Vivado project is atworkspace/project_reti_logiche/project_reti_logiche.vhd

This is the assigned specification for the project:

Project specification 🇮🇹

Original PDF version 🇮🇹

Reference article 🇬🇧 E. Musoll, T. Lang and J. Cortadella, "Working-zone encoding for reducing the energy in microprocessor address buses", inIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 4, pp. 568-572, Dec. 1998