@@ -599,25 +599,20 @@ Status DequantizeLinear<T>::Compute(OpKernelContext* ctx) const {
599599 .TypeConstraint(" T2"
600600 QuantizeLinear<T>);
601601
602- // Opset 23 — aligns with ONNX schema parameter names:
603- // T1 = X
604- // T2 = Y_scale
605- // T3 = Y / Y_zero_point (quantized output)
606- #define REGISTER_QUANTIZELINEAR_OPSET23 (T ) \
607- ONNX_CPU_OPERATOR_VERSIONED_TYPED_KERNEL ( \
608- QuantizeLinear, \
609- 23 , \
610- 23 , \
611- T, \
612- KernelDefBuilder () \
613- .TypeConstraint(" T1" float >(), \
614- DataTypeImpl::GetTensorType<MLFloat16>()}) \
615- .TypeConstraint(" T2" float >(), \
616- DataTypeImpl::GetTensorType<MLFloat16>()}) \
617- .TypeConstraint(" T3"
602+ #define REGISTER_QUANTIZELINEAR_VERSIONED_POST_22 (T ) \
603+ ONNX_CPU_OPERATOR_VERSIONED_TYPED_KERNEL ( \
604+ QuantizeLinear, \
605+ 23 , \
606+ 23 , \
607+ T, \
608+ KernelDefBuilder () \
609+ .TypeConstraint(" T1" float >(), \
610+ DataTypeImpl::GetTensorType<MLFloat16>()}) \
611+ .TypeConstraint(" T2" float >(), \
612+ DataTypeImpl::GetTensorType<MLFloat16>()}) \
613+ .TypeConstraint(" T3"
618614 QuantizeLinear<T>)
619615
620-
621616#define REGISTER_QUANTIZELINEAR_VERSIONED (T, start_version, end_version ) \
622617ONNX_CPU_OPERATOR_VERSIONED_TYPED_KERNEL ( \
623618 QuantizeLinear, \
@@ -665,19 +660,18 @@ REGISTER_QUANTIZELINEAR(Float8E5M2)
665660REGISTER_QUANTIZELINEAR(Float8E5M2FNUZ)
666661#endif
667662
668-
669663// Opset 23
670- REGISTER_QUANTIZELINEAR_OPSET23 (int8_t )
671- REGISTER_QUANTIZELINEAR_OPSET23 (uint8_t )
672- REGISTER_QUANTIZELINEAR_OPSET23 (int16_t )
673- REGISTER_QUANTIZELINEAR_OPSET23 (uint16_t )
674- REGISTER_QUANTIZELINEAR_OPSET23 (Int4x2)
675- REGISTER_QUANTIZELINEAR_OPSET23 (UInt4x2)
664+ REGISTER_QUANTIZELINEAR_VERSIONED_POST_22 (int8_t )
665+ REGISTER_QUANTIZELINEAR_VERSIONED_POST_22 (uint8_t )
666+ REGISTER_QUANTIZELINEAR_VERSIONED_POST_22 (int16_t )
667+ REGISTER_QUANTIZELINEAR_VERSIONED_POST_22 (uint16_t )
668+ REGISTER_QUANTIZELINEAR_VERSIONED_POST_22 (Int4x2)
669+ REGISTER_QUANTIZELINEAR_VERSIONED_POST_22 (UInt4x2)
676670#if !defined(DISABLE_FLOAT8_TYPES)
677- REGISTER_QUANTIZELINEAR_OPSET23 (Float8E4M3FN)
678- REGISTER_QUANTIZELINEAR_OPSET23 (Float8E4M3FNUZ)
679- REGISTER_QUANTIZELINEAR_OPSET23 (Float8E5M2)
680- REGISTER_QUANTIZELINEAR_OPSET23 (Float8E5M2FNUZ)
671+ REGISTER_QUANTIZELINEAR_VERSIONED_POST_22 (Float8E4M3FN)
672+ REGISTER_QUANTIZELINEAR_VERSIONED_POST_22 (Float8E4M3FNUZ)
673+ REGISTER_QUANTIZELINEAR_VERSIONED_POST_22 (Float8E5M2)
674+ REGISTER_QUANTIZELINEAR_VERSIONED_POST_22 (Float8E5M2FNUZ)
681675#endif
682676
683677// Opset 21 added 16-bit and 4-bit int support to Q ops.