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Commit037bc58

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Merge pull request#53 from wnienhaus/fixes-for-v1
Last fixes for v1
2 parents02e94ba +e6ba353 commit037bc58

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3 files changed

+126
-21
lines changed

3 files changed

+126
-21
lines changed

‎esp32_ulp/opcodes.py‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -358,9 +358,7 @@ def get_cond(arg):
358358

359359
def_soc_reg_to_ulp_periph_sel(reg):
360360
# Map SoC peripheral register to periph_sel field of RD_REG and WR_REG instructions.
361-
ifreg<DR_REG_MAX_DIRECT:
362-
ret=RD_REG_PERIPH_RTC_CNTL
363-
elifreg<DR_REG_RTCCNTL_BASE:
361+
ifreg<DR_REG_RTCCNTL_BASE:
364362
raiseValueError("invalid register base")
365363
elifreg<DR_REG_RTCIO_BASE:
366364
ret=RD_REG_PERIPH_RTC_CNTL
@@ -377,11 +375,12 @@ def _soc_reg_to_ulp_periph_sel(reg):
377375

378376
defi_reg_wr(reg,high_bit,low_bit,val):
379377
reg=get_imm(reg)
380-
ifreg<DR_REG_MAX_DIRECT:# see https://github.com/espressif/binutils-esp32ulp/blob/master/gas/config/tc-esp32ulp_esp32.c
381-
_wr_reg.addr=reg
378+
ifreg<=DR_REG_MAX_DIRECT:# see https://github.com/espressif/binutils-esp32ulp/blob/master/gas/config/tc-esp32ulp_esp32.c
379+
_wr_reg.addr=reg&0xff
380+
_wr_reg.periph_sel= (reg&0x300)>>8
382381
else:
383382
_wr_reg.addr= (reg&0xff)>>2
384-
_wr_reg.periph_sel=_soc_reg_to_ulp_periph_sel(reg)
383+
_wr_reg.periph_sel=_soc_reg_to_ulp_periph_sel(reg)
385384
_wr_reg.data=get_imm(val)
386385
_wr_reg.low=get_imm(low_bit)
387386
_wr_reg.high=get_imm(high_bit)
@@ -391,11 +390,12 @@ def i_reg_wr(reg, high_bit, low_bit, val):
391390

392391
defi_reg_rd(reg,high_bit,low_bit):
393392
reg=get_imm(reg)
394-
ifreg<DR_REG_MAX_DIRECT:# see https://github.com/espressif/binutils-esp32ulp/blob/master/gas/config/tc-esp32ulp_esp32.c
395-
_rd_reg.addr=reg
393+
ifreg<=DR_REG_MAX_DIRECT:# see https://github.com/espressif/binutils-esp32ulp/blob/master/gas/config/tc-esp32ulp_esp32.c
394+
_rd_reg.addr=reg&0xff
395+
_rd_reg.periph_sel= (reg&0x300)>>8
396396
else:
397397
_rd_reg.addr= (reg&0xff)>>2
398-
_rd_reg.periph_sel=_soc_reg_to_ulp_periph_sel(reg)
398+
_rd_reg.periph_sel=_soc_reg_to_ulp_periph_sel(reg)
399399
_rd_reg.unused=0
400400
_rd_reg.low=get_imm(low_bit)
401401
_rd_reg.high=get_imm(high_bit)

‎tests/02_compat_rtc_tests.sh‎

Lines changed: 48 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,42 @@ build_defines_db() {
5151
esp-idf/components/esp_common/include/*.h1>$log_file
5252
}
5353

54+
patch_test() {
55+
local test_name=$1
56+
local out_file="${test_name}.tmp"
57+
58+
if ["${test_name}"= esp32ulp_jumpr ];then
59+
(
60+
cd binutils-esp32ulp/gas/testsuite/gas/esp32ulp/esp32
61+
cp${test_name}.s${out_file}
62+
echo -e"\tPatching test to work around binutils-esp32ulp .global bug"
63+
cat>>${out_file}<<EOF
64+
.global check_jump1
65+
EOF
66+
)
67+
return 0
68+
69+
elif ["${test_name}"= esp32ulp_ranges ];then
70+
(
71+
cd binutils-esp32ulp/gas/testsuite/gas/esp32ulp/esp32
72+
# merge 2 files: https://github.com/espressif/binutils-esp32ulp/blob/249ec34/gas/testsuite/gas/esp32ulp/esp32/check_as_ld.sh#L31
73+
echo -e"\t${test_name} requires esp32ulp_globals. Merging both files into${out_file}"
74+
cat esp32ulp_globals.s${test_name}.s>${out_file}
75+
echo -e"\tPatching test to work around binutils-esp32ulp .global bug"
76+
cat>>${out_file}<<EOF
77+
.global min_add
78+
.global min_jump1
79+
.global max_jump1
80+
.global min_jumpr1
81+
.global max_jumpr1
82+
EOF
83+
)
84+
return 0
85+
fi
86+
87+
return 1# nothing was patched
88+
}
89+
5490
make_log_dir
5591
fetch_esp_idf
5692
fetch_ulptool_examples
@@ -60,21 +96,12 @@ build_defines_db $1
6096
forsrc_filein ulptool/src/ulp_examples/*/*.s binutils-esp32ulp/gas/testsuite/gas/esp32ulp/esp32/*.s;do
6197

6298
src_name="${src_file%.s}"
99+
src_dir="${src_name%/*}"
63100

64101
echo"Testing$src_file"
65102

66103
test_name="${src_name##*/}"
67104

68-
# for now, skip files that contain known bugs in esp32_ulp (essentially a todo list of what to fix)
69-
forIin esp32ulp_jumpr esp32ulp_ranges;do
70-
if ["${test_name}"="$I" ];then
71-
# these are old bugs, and not related to the RTC macro handling functionality
72-
# they will still be great to fix over time
73-
echo -e"\tSkipping... known bugs in esp32_ulp"
74-
continue 2
75-
fi
76-
done
77-
78105
# for now, skip files that contain unsupported things (macros)
79106
forIin i2c i2c_dev stack i2c_wr test1 test_jumpr test_macro;do
80107
if ["${test_name}"="$I" ];then
@@ -83,8 +110,18 @@ for src_file in ulptool/src/ulp_examples/*/*.s binutils-esp32ulp/gas/testsuite/g
83110
fi
84111
done
85112

86-
echo -e"\tBuilding using py-esp32-ulp"
113+
# BEGIN: work around known issues with binutils-esp32ulp
87114
ulp_file="${src_name}.ulp"
115+
116+
if patch_test${test_name};then
117+
# switch to the patched file instead of original one
118+
src_file="${src_dir}/${test_name}.tmp"
119+
src_name="${src_file%.tmp}"
120+
ulp_file="${src_name}.tmp.ulp"# when extension is not .s, py-esp32-ulp doesn't remove original extension
121+
fi
122+
# END: work around known issues with binutils-esp32ulp
123+
124+
echo -e"\tBuilding using py-esp32-ulp"
88125
log_file="${src_name}.log"
89126
micropython -m esp32_ulp$src_file1>$log_file# generates $ulp_file
90127

‎tests/opcodes.py‎

Lines changed: 69 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -108,10 +108,78 @@ def assert_raises(exception, func, *args):
108108
assertraised
109109

110110

111+
deftest_reg_direct_ulp_addressing():
112+
"""
113+
Test direct ULP addressing of peripheral registers
114+
input must be <= 0x3ff (10 bits)
115+
periph_sel == high 2 bits from input
116+
addr == low 8 bits from input
117+
"""
118+
119+
ins=make_ins("""
120+
addr : 8 # Address within either RTC_CNTL, RTC_IO, or SARADC
121+
periph_sel : 2 # Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2)
122+
unused : 8 # Unused
123+
low : 5 # Low bit
124+
high : 5 # High bit
125+
opcode : 4 # Opcode (OPCODE_RD_REG)
126+
""")
127+
128+
ins.all=opcodes.i_reg_rd("0x0","0","0")
129+
assertins.periph_sel==0
130+
assertins.addr==0x0
131+
132+
ins.all=opcodes.i_reg_rd("0x012","0","0")
133+
assertins.periph_sel==0
134+
assertins.addr==0x12
135+
136+
ins.all=opcodes.i_reg_rd("0x123","0","0")
137+
assertins.periph_sel==1
138+
assertins.addr==0x23
139+
140+
ins.all=opcodes.i_reg_rd("0x2ee","0","0")
141+
assertins.periph_sel==2
142+
assertins.addr==0xee
143+
144+
ins.all=opcodes.i_reg_rd("0x3ff","0","0")
145+
assertins.periph_sel==3
146+
assertins.addr==0xff
147+
148+
# anything bigger than 0x3ff must be a valid full address
149+
assert_raises(ValueError,opcodes.i_reg_rd,"0x400","0","0")
150+
151+
152+
deftest_reg_address_translations():
153+
"""
154+
Test addressing of peripheral registers using full DPORT bus addresses
155+
"""
156+
157+
ins=make_ins("""
158+
addr : 8 # Address within either RTC_CNTL, RTC_IO, or SARADC
159+
periph_sel : 2 # Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2)
160+
unused : 8 # Unused
161+
low : 5 # Low bit
162+
high : 5 # High bit
163+
opcode : 4 # Opcode (OPCODE_RD_REG)
164+
""")
165+
166+
# direct ULP address is derived from full address as follows:
167+
# full:0x3ff484a8 == ulp:(0x3ff484a8-DR_REG_RTCCNTL_BASE) / 4
168+
# full:0x3ff484a8 == ulp:(0x3ff484a8-0x3ff48000) / 4
169+
# full:0x3ff484a8 == ulp:0x4a8 / 4
170+
# full:0x3ff484a8 == ulp:0x12a
171+
# see: https://github.com/espressif/binutils-esp32ulp/blob/249ec34/gas/config/tc-esp32ulp_esp32.c#L149
172+
ins.all=opcodes.i_reg_rd("0x3ff484a8","0","0")
173+
assertins.periph_sel==1# high 2 bits of 0x12a
174+
assertins.addr==0x2a# low 8 bits of 0x12a
175+
176+
111177
test_make_ins_struct_def()
112178
test_make_ins()
113179
test_arg_qualify()
114180
test_get_reg()
115181
test_get_imm()
116182
test_get_cond()
117-
test_eval_arg()
183+
test_eval_arg()
184+
test_reg_direct_ulp_addressing()
185+
test_reg_address_translations()

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