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SPI master and SPI slave for FPGA written in VHDL
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jakubcabal/spi-fpga
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TheSPI master andSPI slave are simple controllers for communication between FPGA and various peripherals via the SPI interface. The SPI master and SPI slave have been implemented using VHDL 93 and are applicable to any FPGA.
The SPI master and SPI slave controllers support only SPI mode 0 (CPOL=0, CPHA=0)!
The SPI master and SPI slave controllers were simulated and tested in hardware. I use the GHDL tool for CI: automated VHDL simulations in the GitHub Actions environment (setup-ghdl-ci). If you have a question or an improvement tip, send me an e-mail or create an issue.
CLK_FREQ :natural:=50e6;-- set system clock frequency in HzSCLK_FREQ :natural:=5e6;-- set SPI clock frequency in Hz (condition: SCLK_FREQ <= CLK_FREQ/10)WORD_SIZE :natural:=8;-- size of transfer word in bits, must be power of twoSLAVE_COUNT :natural:=1-- count of SPI slaves
CLK :instd_logic;-- system clockRST :instd_logic;-- high active synchronous reset-- SPI MASTER INTERFACESCLK :outstd_logic;-- SPI clockCS_N :outstd_logic_vector(SLAVE_COUNT-1downto0);-- SPI chip select, active in lowMOSI :outstd_logic;-- SPI serial data from master to slaveMISO :instd_logic;-- SPI serial data from slave to master-- INPUT USER INTERFACEDIN :instd_logic_vector(WORD_SIZE-1downto0);-- data for transmission to SPI slaveDIN_ADDR :instd_logic_vector(natural(ceil(log2(real(SLAVE_COUNT))))-1downto0);-- SPI slave addressDIN_LAST :instd_logic;-- when DIN_LAST = 1, last data word, after transmit will be asserted CS_NDIN_VLD :instd_logic;-- when DIN_VLD = 1, data for transmission are validDIN_RDY :outstd_logic;-- when DIN_RDY = 1, SPI master is ready to accept valid data for transmission-- OUTPUT USER INTERFACEDOUT :outstd_logic_vector(WORD_SIZE-1downto0);-- received data from SPI slaveDOUT_VLD :outstd_logic-- when DOUT_VLD = 1, received data are valid
| LE | FF | M9K | Fmax |
|---|---|---|---|
| 34 | 23 | 0 | 330.1 MHz |
Implementation was performed using Quartus Prime Lite Edition 20.1.0 for Intel Cyclone 10 FPGA (10CL025YU256C8G) with default generics.
A simulation is prepared in thesim/ folder. You can use the prepared TCL script to run simulation in ModelSim.
vsim -do spi_master_tb_msim_run.tclOr it is possible to run the simulation using theGHDL tool. Linux users can use the prepared bash script to run the simulation in GHDL:
./spi_master_tb_ghdl_run.shWORD_SIZE :natural:=8;-- size of transfer word in bits, must be power of two
CLK :instd_logic;-- system clockRST :instd_logic;-- high active synchronous reset-- SPI SLAVE INTERFACESCLK :instd_logic;-- SPI clockCS_N :instd_logic;-- SPI chip select, active in lowMOSI :instd_logic;-- SPI serial data from master to slaveMISO :outstd_logic;-- SPI serial data from slave to master-- USER INTERFACEDIN :instd_logic_vector(WORD_SIZE-1downto0);-- data for transmission to SPI masterDIN_VLD :instd_logic;-- when DIN_VLD = 1, data for transmission are validDIN_RDY :outstd_logic;-- when DIN_RDY = 1, SPI slave is ready to accept valid data for transmissionDOUT :outstd_logic_vector(WORD_SIZE-1downto0);-- received data from SPI masterDOUT_VLD :outstd_logic-- when DOUT_VLD = 1, received data are valid
| LE | FF | M9K | Fmax |
|---|---|---|---|
| 29 | 21 | 0 | 324.5 MHz |
Implementation was performed using Quartus Prime Lite Edition 20.1.0 for Intel Cyclone 10 FPGA (10CL025YU256C8G) with default generics.
A simulation is prepared in thesim/ folder. You can use the prepared TCL script to run simulation in ModelSim.
vsim -do spi_slave_tb_msim_run.tclOr it is possible to run the simulation using theGHDL tool. Linux users can use the prepared bash script to run the simulation in GHDL:
./spi_slave_tb_ghdl_run.shTheSpirit Level example design shows one possible use of the SPI Master controller. The example design is prepared forFPGA board CYC1000 with Intel Cyclone 10 FPGA (10CL025YU256C8G) anddigital accelerometer (LIS3DH). Here you can findthe documentation of the CYC1000 board. In this design, the SPI Master controller is used to configure and read data from the accelerometer. The LEDs on the board show the values from the accelerometer in the form of a spirit level. You can watch the Spirit Level examplevideo on YouTube.
TheSPI loopback example design allows testing transfers between SPI master and SPI slave over external wires. The example design is prepared for FPGA boardEP4CE6 Starter Board with Altera FPGA Cyclone IV (EP4CE6E22C8), few buttons and a seven-segment display (four digit). You can watch the SPI loopback examplevideo on YouTube.
Display description (from right on board in video):
Digit0 = value on SPI slave inputDigit1 = value on SPI slave outputDigit2 = value on SPI master inputDigit3 = value on SPI master outputButtons description (from right on board in video):
BTN_ACTION (in mode0) = setup value on SPI slave inputBTN_ACTION (in mode1) = write (set valid) of SPI slave input valueBTN_ACTION (in mode2) = setup value on SPI master inputBTN_ACTION (in mode3) = write (set valid) of SPI slave input value and start transfer between SPI master and SPI slaveBTN_MODE = switch between modes (mode0 = light decimal point on digit0,...)BTN_RESET = reset FPGA designThis whole repository (include SPI master and SPI slave controllers) is available under the MIT license. Please readLICENSE file.
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SPI master and SPI slave for FPGA written in VHDL