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1. friscvfriscvPublic

   RISCV CPU implementation in SystemVerilog

   SystemVerilog 32 6

2. svutsvutPublic

   SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

   Python 79 17

3. bsterbsterPublic

   Implementation of a binary search tree algorithm in a FPGA/ASIC IP

   SystemVerilog 20 5

4. async_fifoasync_fifoPublic

   A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

   Verilog 386 93

5. axi-crossbaraxi-crossbarPublic

   An AXI4 crossbar implementation in SystemVerilog

   SystemVerilog 178 31

6. svloggersvloggerPublic

   SystemVerilog Logger

   SystemVerilog 18 2