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Welcome to Verilator, the fastest Verilog/SystemVerilog simulator. Accepts Verilog or SystemVerilog Performs lint code-quality checks Compiles into multithreaded C++, or SystemC Creates XML to front-end your own tools
	Fast Outperforms many closed-source commercial simulators Single- and multithreaded output models
Widely Used Wide industry and academic deployment Out-of-the-box support from Arm and RISC-V vendor IP
	Community Driven & Openly Licensed Guided by theCHIPS Alliance andLinux Foundation Open, and free as in both speech and beer More simulation for your verification budget
Commercial Support Available Commercial support contracts Design support contracts Enhancement contracts

Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It"Verilates" the specified Verilog or SystemVerilog code by reading it,performing lint checks, and optionally inserting assertion checks andcoverage-analysis points. It outputs single- or multithreaded .cpp and .hfiles, the "Verilated" code.

These Verilated C++/SystemC files are then compiled by a C++ compiler(gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapperfile, to instantiate the Verilated model. Executing the resultingexecutable performs the design simulation. Verilator also supports linkingVerilated generated libraries, optionally encrypted, into other simulators.

Verilator may not be the best choice if you are expecting a full-featuredreplacement for a closed-source Verilog simulator, need SDF annotation,mixed-signal simulation, or are doing a quick class project (we recommendIcarus Verilog for classwork). However, if you are looking for a pathto migrate SystemVerilog to C++/SystemC, or want high-speed simulation ofdesigns, Verilator is the tool for you.

Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather,Verilator compiles your code into a much faster optimized and optionallythread-partitioned model, which is in turn wrapped inside a C++/SystemCmodule. The results are a compiled Verilog model that executes even on asingle thread over 10x faster than standalone SystemC, and on a singlethread is about 100 times faster than interpreted Verilog simulators suchasIcarus Verilog. Another 2-10x speedup might be gained frommultithreading (yielding 200-1000x total over interpreted simulators).

Verilator has typically similar or better performance versus closed-sourceVerilog simulators (e.g., Aldec Riviera-Pro, Cadence Incisive/NC-Verilog,Mentor ModelSim/Questa, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But,Verilator is open-sourced, so you can spend on computes rather thanlicenses. Thus, Verilator gives you the best simulation cycles/dollar.

For more information:

• Verilator installation and package directory structure
• Verilator manual (HTML),orVerilator manual (PDF)
• Subscribe to Verilator announcements
• Verilator forum
• Verilator issues

Verilator is a community project, guided by theCHIPS Alliance under theLinux Foundation.

We appreciate and welcome your contributions in whatever form; please seeContributing to Verilator.Thanks to ourContributors and Sponsors.

Verilator also supports and encourages commercial support models andorganizations; please seeVerilator Commercial Support.

• GTKwave - Waveform viewer forVerilator traces.
• Icarus Verilog - Icarus is a highly-featured interpreted Verilogsimulator. If Verilator does not support your needs, perhaps Icarus may.

Verilator is Copyright 2003-2025 by Wilson Snyder. (Report bugs toVerilator Issues.)

Verilator is free software; you can redistribute it and/or modify it underthe terms of either the GNU Lesser General Public License Version 3 or thePerl Artistic License Version 2.0. See the documentation for more details.