CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems

🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open sourceProjects, which areWorkgroups.

Popular repositoriesLoading

chiselchiselPublic
Chisel: A Modern Hardware Design Language
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rocket-chiprocket-chipPublic
Rocket Chip Generator
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veribleveriblePublic
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
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riscv-dvriscv-dvPublic
Random instruction generator for RISC-V processor verification
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Cores-VeeR-EH1Cores-VeeR-EH1Public
VeeR EH1 core
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firrtlfirrtlPublic archive
Flexible Intermediate Representation for RTL
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Repositories

Showing 10 of 109 repositories

sv-tests Public
Test suite designed to check compliance with the SystemVerilog standard.
chipsalliance/sv-tests’s past year of commit activity
SystemVerilog 310ISC 78 47 (5 issues need help) 12 UpdatedMar 31, 2025
Caliptra Public
Caliptra IP and firmware for integrated Root of Trust block
chipsalliance/Caliptra’s past year of commit activity
276Apache-2.0 40 42 7 UpdatedMar 31, 2025
caliptra-sw Public
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
chipsalliance/caliptra-sw’s past year of commit activity
Rust 108Apache-2.0 52 124 56 UpdatedMar 31, 2025
caliptra-ss Public
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
chipsalliance/caliptra-ss’s past year of commit activity
SystemVerilog 13Apache-2.0 9 48 13 UpdatedMar 31, 2025
t1 Public
chipsalliance/t1’s past year of commit activity
Scala 261Apache-2.0 34 19 34 UpdatedMar 31, 2025
rvdecoderdb Public
The Scala parser to parse riscv/riscv-opcodes generate
chipsalliance/rvdecoderdb’s past year of commit activity
Nix 16 6 1 3 UpdatedMar 31, 2025
sv-tests-results Public
Output of the sv-tests runs.
chipsalliance/sv-tests-results’s past year of commit activity
HTML 5 3 0 0 UpdatedMar 31, 2025
rocket-chip Public
Rocket Chip Generator
chipsalliance/rocket-chip’s past year of commit activity
Scala 3,391 1,159 241 65 UpdatedMar 31, 2025
verible Public
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
chipsalliance/verible’s past year of commit activity
C++ 1,500 229 501 (15 issues need help) 23 UpdatedMar 30, 2025
i3c-core Public
chipsalliance/i3c-core’s past year of commit activity
SystemVerilog 19Apache-2.0 5 9 0 UpdatedMar 30, 2025