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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open sourceProjects, which areWorkgroups.

Popular repositoriesLoading

chiselchiselPublic
Chisel: A Modern Hardware Design Language
Scala 4.3k 631
rocket-chiprocket-chipPublic
Rocket Chip Generator
Scala 3.5k 1.2k
veribleveriblePublic
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
C++ 1.6k 243
riscv-dvriscv-dvPublic
Random instruction generator for RISC-V processor verification
Python 1.1k 350
Cores-VeeR-EH1Cores-VeeR-EH1Public
VeeR EH1 core
SystemVerilog 884 230
firrtlfirrtlPublic archive
Flexible Intermediate Representation for RTL
Scala 746 181

Showing 10 of 110 repositories

adams-bridge Public
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
chipsalliance/adams-bridge’s past year of commit activity
SystemVerilog 30Apache-2.0 7 14 4 UpdatedJul 8, 2025
caliptra-ss Public
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
chipsalliance/caliptra-ss’s past year of commit activity
SystemVerilog 23Apache-2.0 21 39 5 UpdatedJul 8, 2025
caliptra-sw Public
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
chipsalliance/caliptra-sw’s past year of commit activity
Rust 119Apache-2.0 63 148 60 UpdatedJul 8, 2025
i3c-core Public
chipsalliance/i3c-core’s past year of commit activity
SystemVerilog 30Apache-2.0 9 4 1 UpdatedJul 8, 2025
t1 Public
chipsalliance/t1’s past year of commit activity
Scala 276Apache-2.0 38 18 25 UpdatedJul 8, 2025
Caliptra Public
Caliptra IP and firmware for integrated Root of Trust block
chipsalliance/Caliptra’s past year of commit activity
308Apache-2.0 47 45 6 UpdatedJul 8, 2025
sv-tests Public
Test suite designed to check compliance with the SystemVerilog standard.
chipsalliance/sv-tests’s past year of commit activity
SystemVerilog 331ISC 82 48 (5 issues need help) 22 UpdatedJul 7, 2025
sv-tests-results Public
Output of the sv-tests runs.
chipsalliance/sv-tests-results’s past year of commit activity
HTML 7 6 0 0 UpdatedJul 8, 2025
caliptra-mcu-sw Public
Caliptra MCU Software
chipsalliance/caliptra-mcu-sw’s past year of commit activity
Rust 15Apache-2.0 11 21 3 UpdatedJul 8, 2025
caliptra-dpe Public
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
chipsalliance/caliptra-dpe’s past year of commit activity
Rust 17Apache-2.0 26 12 8 UpdatedJul 7, 2025