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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open sourceProjects, which areWorkgroups.

Popular repositoriesLoading

chiselchiselPublic
Chisel: A Modern Hardware Design Language
Scala 4.2k 621
rocket-chiprocket-chipPublic
Rocket Chip Generator
Scala 3.4k 1.2k
veribleveriblePublic
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
C++ 1.5k 231
riscv-dvriscv-dvPublic
Random instruction generator for RISC-V processor verification
Python 1.1k 336
Cores-VeeR-EH1Cores-VeeR-EH1Public
VeeR EH1 core
SystemVerilog 865 228
firrtlfirrtlPublic archive
Flexible Intermediate Representation for RTL
Scala 740 180

Showing 10 of 110 repositories

chips-alliance-website Public
chipsalliance/chips-alliance-website’s past year of commit activity
SCSS 4MIT 5 8 8 UpdatedApr 4, 2025
sv-tests Public
Test suite designed to check compliance with the SystemVerilog standard.
chipsalliance/sv-tests’s past year of commit activity
SystemVerilog 311ISC 78 47 (5 issues need help) 14 UpdatedApr 4, 2025
caliptra-sw Public
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
chipsalliance/caliptra-sw’s past year of commit activity
Rust 109Apache-2.0 53 130 57 UpdatedApr 4, 2025
caliptra-rtl Public
HW Design Collateral for Caliptra RoT IP
chipsalliance/caliptra-rtl’s past year of commit activity
SystemVerilog 87Apache-2.0 47 93 11 UpdatedApr 4, 2025
Cores-VeeR-EL2 Public
VeeR EL2 Core
chipsalliance/Cores-VeeR-EL2’s past year of commit activity
SystemVerilog 270Apache-2.0 81 19 0 UpdatedApr 4, 2025
Caliptra Public
Caliptra IP and firmware for integrated Root of Trust block
chipsalliance/Caliptra’s past year of commit activity
276Apache-2.0 40 43 7 UpdatedApr 4, 2025
sv-tests-results Public
Output of the sv-tests runs.
chipsalliance/sv-tests-results’s past year of commit activity
HTML 6 3 0 0 UpdatedApr 4, 2025
verilator Public Forked fromverilator/verilator
Verilator open-source SystemVerilog simulator and lint system
chipsalliance/verilator’s past year of commit activity
C++ 37LGPL-3.0 655 0 0 UpdatedApr 4, 2025
chisel Public
Chisel: A Modern Hardware Design Language
chipsalliance/chisel’s past year of commit activity
Scala 4,227Apache-2.0 621 329 (1 issue needs help) 158 UpdatedApr 4, 2025
t1 Public
chipsalliance/t1’s past year of commit activity
Scala 263Apache-2.0 34 19 37 UpdatedApr 4, 2025