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Add -blackbox option to cutpoint pass#4854

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@KrystalDelusionKrystalDelusion commentedJan 16, 2025
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What are the reasons/motivation for this change?
Supersedes#4812.

Explain how this is achieved.
Callingcutpoint -blackbox [options] will replace the contents of all (black)boxes in the design with a formal cut point ($anyseq cell by default).
This is preferable to#4812, which instead callscutpoint on instances of (black)box modules.
Since the module now has contents, it is also no longer a (black)box so we can remove those attributes.

If applicable, please suggest to reviewers how they can test the change.

Replace the contents of all blackboxes in the design with a formal cut point.Includes test script.
Also adds "blackbox" as a valid TYPE.
Modify `cutpoint_blackbox.ys` to check that parameters on blackbox modules are maintained after the cutpoint.Also adjusts the test to check that each instance gets the `$anyseq` cell.
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From#4812:

This way we avoid any problems with needing to derive de-blackboxed modules to handle I/O signals with parametrizable widths, which isn't possible when they came from verific.

So I take it this new approach doesn't support parametrizable widths.

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Uhhh, pass?

moduletop(input a, b,output o);wire c, d, e, f;bb #(.SOME_PARAM(1))bb1 (.a (a), .b (b), .o (c));wbwb1 (.a (a), .b (b), .o (d));bb #(.SOME_PARAM(2))bb2 (.a ({a,b}), .b ({c,d}), .o ({e,f}));some_modsome_inst (.a (c), .b (d), .c (e), .o (o));endmodule(* blackbox*)modulebb #(parameter SOME_PARAM=0 ) (input [SOME_PARAM-1:0] a, b,output [SOME_PARAM-1:0] o);assign o= a| b;specify(a=> o)=1;endspecifyendmodule(* whitebox*)modulewb(input a, b,output o);assign o= a ^ b;endmodule(* keep_hierarchy*)modulesome_mod(input a, b, c,output o);assign o= a& (b| c);endmodule
read -vlog2k cutpoint_blackbox.vhierarchy -top topcutpoint -blackboxflattenopt -purge

cut

read -vlog2k cutpoint_blackbox.vhierarchy -top topselect topsetundef -blackbox -anyseq

set

@KrystalDelusion
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I'm not seeing any change in behaviour there; the$anyseq cells for thebb module are both 2bit wide when coming from verific using both thecutpoint andsetundef versions of this.

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I understood inserting the$anyseq cells on blackbox outputs without going the flatten route was motivated by making parametrizable widths work with Verific. Since this PR now has a different approach I'm wondering if parametrizable widths dropped from the requirements

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I don't have any examples that demonstrate whatever problems are being encountered with the current options when it comes to blackboxes in verific, but as far as I can tell changing the cell outputs (i.e thesetundef version of this) gives the same result as this when it comes to output widths. In my quick testing it looks like verific sets the port width on the module and all instances of it to the widest required.

Rather than it no longer being required, I would say that if this implementation is not meeting that requirement then I don't see how#4812 was.

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@KrystalDelusion
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I wasn't there for the original dev JF discussion, but when we discussed#4812 in docs JF about whether callingcutpoint from withinsetundef was the right approach we said:

  • Using cutpoint to remove an instance should be equivalent to cutting out all contents of the module and then flattening that module into the module containing the instance (wrt generated $scopeinfo and hdlname attributes)
  • Cutpoint alone can handle all current use cases, let's not put it in setundef for now

(or at least that's what is in the minutes)

@KrystalDelusionKrystalDelusion added the discussto be discussed at next dev jour fixe (see #devel-discuss at https://yosyshq.slack.com/) labelJan 17, 2025
@KrystalDelusionKrystalDelusion marked this pull request as draftJanuary 20, 2025 22:37
Replace module instances instead of module contents.This fixes parametrisable width mismatch with read_verilog frontend, but not verific frontend.
But only if it's also a blackbox module with parameters (i.e. it *could* be parametrizable width).
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I worked out that callinghierarchy with-keep_portwidths prevents changing the cell port width to match the module definition and matches the behaviour betweenread_verilog andverific. It looks like when it comes from read_verilog, the blackbox module has aID::dynports attribute on it which is how the problem gets resolved withread_verilog. So I've added a check tohierarchy which sets a flag (boxed_params) if a cell instantiates a parametrised blackbox module without theID::dynports attribute, and then if that flag is set, a verific module has been loaded, and there's a mismatch in the port size then it raises a warning instead of resizing the port.

I also added an extra flag tocutpoint, so that callingcutpoint -blackbox -instances will replace instances of blackbox modules (a la the approach fromsetundef).

So this does now properly support modules from verific with parametrisable widths,but I'm not sure if there are any cases where skipping the resize could cause problems that would make this unsafe. Also whether the-instances behaviour should be a flag or if I should just remove the other method.

Thoughts,@povik ?

@KrystalDelusionKrystalDelusion removed the discussto be discussed at next dev jour fixe (see #devel-discuss at https://yosyshq.slack.com/) labelJan 28, 2025
@KrystalDelusionKrystalDelusion marked this pull request as ready for reviewJanuary 28, 2025 20:54
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