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Control and status register code generator toolchain

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SystemRDL/PeakRDL

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Documentation StatusbuildCoverage StatusPyPI - Python Version

PeakRDL

PeakRDL is a free and open-source control & status register (CSR) generatortoolchain. This project provides a command-line tool that unifies many aspectsof register automation such as generating Verilog CSR RTL, compiling aC register abstraction layer, and many more. PeakRDL is centered around theSystemRDL register description language, but is also capable of working withother CSR specifications like IP-XACT.

This tool can:

  • Process SystemRDL 2.0 register descriptions.
  • Generate synthesizable SystemVerilog RTL register blocks.
  • Generate a C register abstraction header for software.
  • Import & export IP-XACT XML.
  • Create rich and dynamic HTML documentation.
  • Build a UVM register model abstraction layer.
  • Extend this tool with your own plugin.
  • ... or use one of the manycommunity plugins

Documentation

See thePeakRDL Documentation for more details.


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