The goal of this GitHub organization is to build high-quality free andopen-source tools for control & status register (CSR) automation, and topromoteAccellera's SystemRDLas the language of choice for CSR design entry.1
If you are new to SystemRDL, check outthis quick language tutorial.
PeakRDL is a command-line application that provides a ready-to-use registerautomation toolchain.
See thePeakRDL Documentation for more details.
If the command line tool isn't your style, you can use the PeakRDL componentsindividually. Each component is installable as a separate Python package and hasa documented API you can use to integrate it into your own custom workflow.
- PeakRDL-regblock generates synthesizable SystemVerilog RTL.
- PeakRDL-html produces intuitive and dynamic HTML documentation.
- PeakRDL-uvm generates a UVM register model.
- PeakRDL-ipxact lets you import and export IP-XACT XML.
- PeakRDL-cheader outputs a software abstraction layer C header.
Be sure to also check out the growing list of toolsothers in the community have made.
Need to build something custom? Don'tinvent your ownjanky input format - Use SystemRDL! The SystemRDL compiler front-end handles allthe heavy-lifting of processing the SystemRDL language so you don't have to.The compiler provides a rich and intuitive Python API that you can use for yourown custom register automation.
See theSystemRDL Compiler Documentationfor more details.
If you are just ramping up the use of SystemRDL and still need to support otherinternal register spec formats, it is pretty easy to create an importer to helptransition your workflow from non-SystemRDL spec formats.
To learn how this works, check outthe tutorial on PeakRDL importer plugins.
Footnotes
This SystemRDL GitHub group is not affiliated with Accellera.↩
Popular repositoriesLoading
- PeakRDL-regblock
PeakRDL-regblock PublicGenerate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
- PeakRDL-html
PeakRDL-html PublicGenerate address space documentation HTML from compiled SystemRDL input
Repositories
- PeakRDL-regblock Public
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
SystemRDL/PeakRDL-regblock’s past year of commit activity - PeakRDL-cheader Public
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