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This project focuses on developing a visual memory simulator using ChampSim, an efficient trace-based simulator for microarchitecture research. Our simulator features a graphical user interface (GUI) designed to display the usage of data cache in real-time, providing an interactive way to understand memory access patterns and cache behaviour.

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Smriti-26/Visual-Memory-Simulator

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Visual Memory Simulator (VMS) is a graphical tool designed to visualize cache memory operations and simulate memory access patterns for better understanding of computer architecture concepts.
It supports configurable cache parameters, multiple replacement policies, and interactive visualization utilities.


Installation and Setup

1. Clone the Repository

git clonehttps://github.com/Smriti-26/Visual-Memory-Simulator

2. Navigate into the Project Directory

cd Visual-Memory-Simulator

3. Create and Activate a Virtual Environment

python3 -m venv .venv
source .venv/bin/activate

4. Install Required Dependencies

python3 -m pip install PyQt5
sudo apt-get install libxcb-xinerama0
pip install matplotlib
pip install pyautogui
pip install opencv-python
pip install opencv-python-headless

5. Extract Required Archives

tar -xf pin-3.30-98830-g1d7b601b3-gcc-linux.tar.xz
tar -xf tracer.tar.xz

6. Grant Execution Permissions to ChampSim Scripts

chmod +x run_champsim.sh
chmod +x build_champsim.sh

7. Install VLC to Enable Video Output

sudo apt install vlc -y

8. Run VMS

python3 mainVMS.py

Optional Dependencies

If some dependencies are missing, you may verify or install the following versions:

PackageVersion
contourpy1.2.1
cycler0.12.1
fonttools4.52.4
kiwisolver1.4.5
matplotlib3.9.0
numpy1.26.4
opencv-python4.9.0.80
opencv-python-headless4.10.0.82
packaging24.0
pillow10.3.0
pip24.0
pyparsing3.1.2
PyQt55.15.10
PyQt5-Qt55.15.2
PyQt5-sip12.13.0
python-dateutil2.9.0.post0
six1.16.0

VMS Utilities and Functionalities

Configurable Cache ParametersModify block size, sets, and ways using the Update Parameter button.Execution NoteThe interface may temporarily display “Not Responding” — this indicates background computation, not an error. The display updates automatically when execution completes.Cache Replacement PoliciesSupports LRU and SRRIP, selectable via radio buttons.Graph and Video GenerationEnable the “Create Graph” and “Create Video” checkboxes after running a simulation to visualize cache activity.Input OptionsEnter C/C++ code directly in the text box, or upload a .c / .cpp file, or select a pre-generated trace file.VisualizationThe color gradient ribbon represents cache block usage:    🟡 Yellow → Minimum access frequency    🔴 Red → Maximum access frequencyScreenshot FunctionalityCapture the simulator window anytime using the Take Screenshot button.Reset FunctionReset the cache state using the Reset button.Run FunctionExecute the program, generate a trace file, and visualize the final cache condition using the Run button.Next Access VisualizationView the cache state after the next memory access using the Next button, based on the skip instruction count.Skip Instruction CountDefines how many instructions are skipped before showing the next memory access.Write ToleranceSpecifies how many times a cache block can be accessed before it is considered worn out.

Authors and Contributors

Smriti GuptaIndian Institute of Technology, RoparGitHub: Smriti-26Sushant Arun BhaleraoIndian Institute of Technology, RoparGitHub: Sushant0001Under the guidance of:Dr. Neeraj Goel and Dr. T. V. Kalyan

Notes

The tool is computationally intensive — expect slight delays during large simulations.Ensure all extracted directories (e.g., pin, tracer) are located within the project folder.For any issues or contributions, please visit the GitHub Repository

About

This project focuses on developing a visual memory simulator using ChampSim, an efficient trace-based simulator for microarchitecture research. Our simulator features a graphical user interface (GUI) designed to display the usage of data cache in real-time, providing an interactive way to understand memory access patterns and cache behaviour.

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