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32 - bit floating point Multiplier Accumulator Unit (MAC)

The proposed MAC unit is implemented in Xilinx ISE Design suite 2018.2 on ZedBoard Zynq Evaluation and Development Kit (xc7z020clg484-1).Both Floating Point adder and multiplier are fully synthesizable.The above approach has been adapted from [Implementation of 32 Bit Floating Point MAC Unit to Feed Weighted Inputs to Neural Networks].

The result can be verified from the screenshot here.