You can find an overview of OSVVM atosvvm.github.io.Alternately you can find our pdf documentation atOSVVM Documentation Repository.

You can also learn OSVVM by taking the class,Advanced VHDL Verification and Testbenches - OSVVM™ BootCamp

A great way to get oriented with OSVVM is to run the demos.For directions on running the demos, seeOSVVM Scripts.

OsvvmLibraries contains all other OSVVM repositories as submodules. If you want everything, this is the one you need to clone.

Be sure to use “–recursive” to include the submodules:

  $ git clone --recursive https://github.com/osvvm/OsvvmLibraries

Get a zip file fromosvvm.org Downloads Page.

The OSVVM Utility library (named osvvm) implementsbuzz word verification capabilities including Constrained Random, Functional Coverage,Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filteringthat are simple to use and work like built-in language features.

The OSVVM script library implementsa common scripting API to run all simulators -including GHDL, NVC, Aldec Riviera-PRO and ActiveHDL, Siemens Questa and ModelSim, Synopsys VCS, and Cadence Xcelium.
Our motto: "One Script to RUn them ALL"

The Model Independent Transaction (MIT) library (osvvm_common) defines a transaction API (procedures such as read, write, send, get, …)and transaction interface (a record) that simplifies writing verification components and test cases.The MIT library is used (and required) by all OSVVM verification components.Usi8ng OSVVM MIT makes verification component deveopment as easy as any "Lite" based approach.

The OSVVM Verification Component Libraries are a growing set ofverification components commonly used for FPGA and ASIC verification.Each family of verification components is a separate git repository.The library currently contains the following repositories:

• AXI4 Repository
  • Axi4 Full Manager (burst), Memory (burst), Subordinate Verification Components
  • Axi4 Lite Manager and Subordinate Verification Components
  • AxiStream Transmitter and Receiver Verification Components
• UART Repository
  • UART Transmitter and Receiver
• DpRam Repository
  • DpRam behavioral model
  • DpRam Manager VC to read and write to the DpRam interface
• Ethernet xMII Repository
  • Verification components for Ethernet Phy and MAC that support GMII/RGMII/MII/RMII.

OSVVM co-simulation supports running software (C++) in a hardware simulation environment.
This includes either writing tests cases in C++ or running C++ models such as instruction set simulators.

PDF documentation for all things OSVVM.

Repositories