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Releases: Multimedia-Processing/Digital-Logic-Design

v6.3.6

19 Mar 09:32

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如果採用，此提交將新增使用always製作的clock範例修改項目:此為課本沒有的範例，在此新增。模組:議題61
Assets2
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v6.2.4

23 Oct 08:21

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新增項目:

  • 6 組合邏輯應用實習
    • 6-2 LED七段顯示器與解碼器的實習
      • 工作項目二
      • 工作項目三
      • 工作項目四
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v6.1.5

24 Oct 15:56

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新增項目:

  • 6 組合邏輯應用實習
    • 6-1 編碼器與解碼器的實習
      • 工作項目二
      • 工作項目三
      • 工作項目四
      • 工作項目五
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v5.3.5

09 Sep 15:42
56dd8f9
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新增項目:

  • 5 加法器與減法器實習
    • 5-3 BCD加法器的實習
      • 工作項目二
      • 工作項目三
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v5.3.4

29 Aug 13:31
2a3bd14
This commit was created on GitHub.com and signed with GitHub’sverified signature. The key has expired.
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  • 4 組合邏輯實習
    • 4-1 布林定理、第摩根定理與邏輯閘互換的實習
    • 4-2 積項之和(SOP)式的組合邏輯與化簡實習
    • 4-3 和項之積(POS)式的組合邏輯與化簡實習
  • 5 加法器與減法器實習
    • 5-1 半加器、全加器與並列加法器的實習
    • 5-2 半減器、全減器與並列加法器的實習
    • 5-3 BCD加法器的實習
      • 工作項目一
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v3.2.4

28 Aug 10:05
bab16e7
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完成實習課程:

  • 3 基本邏輯閘實習
    • 3-2 各種基本邏輯閘的功能實習
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