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Simulator of a pipelined, superscalar processor.
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BakerSmithA/processor_sim
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Simulator of a pipelined, superscalar processor.
Clone the repo, and then run the following commands. The compiled output can be found indist/build/vm
.
> cd processor_sim> cabal sandbox init> cabal install> cabal build
The processor runs binary files representing assembly instructions (seeAssembly Instructions). To avoid having to write this manually, the C-- compiler is availablehere which outputs binary for the simulator. To run a compiled binary file, simply supply the filename as an argument to this simulator.
To run the processor, the following stages of the pipeline are run:
- Fetch;N instructions (whereN is the width of the pipeline) are fetched from the instruction cache.
- Decode; instructions are decoded, and destination registers are renamed to remove false dependencies between instructions.
- Execute; instructions are placed in reservation stations, and then run by their corresponding execution unit once all the instructions dependencies have been resolved.
- Commit; instructions are placed in the reorder buffer. This allows instructions to be written back to memory or registers in the same order as they were fetched. This also allows speculatively executed instructions to be discarded.
- Writeback; instructions are written back to memory or registers.
The instruction set consists of 24 instructions. The notation used is:
Symbol | Meaning |
---|---|
r | Register at indexr |
mem[x] | Value of memory at indexx |
#i | Immediate with valuei |
pc | Program counter |
lr | Link Register |
Instruction Mnemonic | Action |
---|---|
LoadIdx r base #off | r <- mem[base + #off] |
LoadBaseIdx r base off | r <- mem[base + off] |
StoreIdx r base #off | mem[base + #off] <- r |
StoreBaseIdx r base off | mem[base + off] <- r |
MoveI r #i | r <- #i |
Move r src | r <- src |
Add r x y | r <- x + y |
AddI r x #i | r <- x + #i |
Sub r x y | r <- x - y |
SubI r x #i | r <- x - #i |
Mult r x y | r <- x * y |
Div r x y | r <- x / y |
Eq r x y | r <- x == y |
Lt r x y | r <- x < y |
Or r x y | r <- x || y |
And r x y | r <- x && y |
Not r x | r <- !x |
B addr | pc <- addr |
BT addr | if (r == 1) then pc <- addr |
BF addr | if (r == 0) then pc <- addr |
Ret | pc <- lr |
SysCall | End execution |
Print r | Print value of registerr to output |
PrintLn | Print a newline to output |
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Simulator of a pipelined, superscalar processor.
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