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Simulator of a pipelined, superscalar processor.

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BakerSmithA/processor_sim

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Simulator of a pipelined, superscalar processor.

Install

Clone the repo, and then run the following commands. The compiled output can be found indist/build/vm.

> cd processor_sim> cabal sandbox init> cabal install> cabal build

Running

The processor runs binary files representing assembly instructions (seeAssembly Instructions). To avoid having to write this manually, the C-- compiler is availablehere which outputs binary for the simulator. To run a compiled binary file, simply supply the filename as an argument to this simulator.

Design

To run the processor, the following stages of the pipeline are run:

  1. Fetch;N instructions (whereN is the width of the pipeline) are fetched from the instruction cache.
  2. Decode; instructions are decoded, and destination registers are renamed to remove false dependencies between instructions.
  3. Execute; instructions are placed in reservation stations, and then run by their corresponding execution unit once all the instructions dependencies have been resolved.
  4. Commit; instructions are placed in the reorder buffer. This allows instructions to be written back to memory or registers in the same order as they were fetched. This also allows speculatively executed instructions to be discarded.
  5. Writeback; instructions are written back to memory or registers.

Assembly Instructions

The instruction set consists of 24 instructions. The notation used is:

SymbolMeaning
rRegister at indexr
mem[x]Value of memory at indexx
#iImmediate with valuei
pcProgram counter
lrLink Register
Instruction MnemonicAction
LoadIdx r base #offr <- mem[base + #off]
LoadBaseIdx r base offr <- mem[base + off]
StoreIdx r base #offmem[base + #off] <- r
StoreBaseIdx r base offmem[base + off] <- r
MoveI r #ir <- #i
Move r srcr <- src
Add r x yr <- x + y
AddI r x #ir <- x + #i
Sub r x yr <- x - y
SubI r x #ir <- x - #i
Mult r x yr <- x * y
Div r x yr <- x / y
Eq r x yr <- x == y
Lt r x yr <- x < y
Or r x yr <- x || y
And r x yr <- x && y
Not r xr <- !x
B addrpc <- addr
BT addrif (r == 1) then pc <- addr
BF addrif (r == 0) then pc <- addr
Retpc <- lr
SysCallEnd execution
Print rPrint value of registerr to output
PrintLnPrint a newline to output

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