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|
 eZ80 in aTI-84 Plus CE with 256 KB on-chip RAM | |
| General information | |
|---|---|
| Launched | 2001[1] |
| Marketed by | Zilog |
| Designed by | Zilog |
| Common manufacturer |
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| Performance | |
| Max.CPUclock rate | to 50 MHz |
| Data width | 8 |
| Address width | 24 |
| Architecture and classification | |
| Instruction set | Z80[a] |
| Extensions |
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| History | |
| Predecessor | Zilog Z80 |
TheZilog eZ80 is an8-bit microprocessor designed byZilog as an updated version of the company's first product, the highly-successfulZilog Z80. The eZ80 isbinary compatible with theZ80 instruction set, but it operates almost three times faster at the sameclock frequency. eZ80 features an optional mode that expands memory addressing to 16 megabytes.
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The eZ80 has a three-stage pipeline: fetch, decode, and execute. When an instruction changes theprogram counter, it flushes the instructions that the CPU is currently processing. Available at up to 50 MHz (2004), the performance is comparable to a Z80 clocked at 150 MHz if fast memory is used (i.e. no wait states foropcode fetches, for data, or for I/O) or even higher in some applications (a 16-bit addition is 11 times as fast as in the original). The original Z80-compatible 16-bit register configuration is supported. The eZ80 also supports direct continuous addressing of 16 MB of memory without amemory management unit, by extending most registers (HL, BC, DE, IX, IY, SP, and PC) from 16 to 24 bits. In order to do so, the CPU has a full 24-bit address mode called ADL mode. In ADL mode, all Z80 16-bit registers are extended to 24 bits with additional upper 8-bit registers. For example, the HL register pair is extended with an uppermost register called HLU. The resulting 24-bit multi-byte register is collectively accessed by its old name, HL. The upper registers cannot be accessed individually.[2] Although the eZ80 handles 24-bit math and moves, it only supports 8-bit operations for logic functions such as AND, OR, and XOR.
The processor has a 24-bitarithmetic unit and overlapped processing of several instructions (the three-stage pipeline) which are the two primary reasons for its speed. Unlike the olderZ280 andZ380 it does not have (or need) a cache memory. Instead, it is intended to work with fastSRAM directly as main memory (as this had become much cheaper). Nor does it have the multiplexed bus of the Z280, making it as easy to work with (interface to) as the original Z80 and Z180, and equally predictable when it comes to exact execution times.
The chip has amemory interface that is similar to the original Z80, including the bus request/acknowledge pins, and adds four integrated chip selects. Versions are available with on-chip flash memory and on-chip zero wait-state SRAM (up to 256 KB flash memory and 16 KB SRAM) but there are also external buses on all models.
The eZ80 family includes several variants offering different levels of integration. These single-chip computers retain an external address and data bus so they can function as general-purpose microprocessors despite their focus on specific applications.
TheeZ80Acclaim! line integrates up to 128 KB of flash memory and 8 KB of SRAM, operating at speeds up to 20 MHz.[3][4]
TheeZ80AcclaimPlus! adds anEthernet controller and TCP/IP stack to the eZ80Acclaim! features, reaching speeds of up to 50 MHz.[5]
TheTI-84 Plus CE graphing calculator utilizes the eZ80 in 24-bit address mode at 48 MHz.[6] The eZ80L92 processor powers theST Robotics robot controller, running at 50 MHz.[7]
