 Logo since 2024 | |
| General information | |
|---|---|
| Launched | June 29, 1998; 27 years ago (June 29, 1998)[1] |
| Marketed by | Intel |
| Designed by | Intel |
| Common manufacturer |
|
| Performance | |
| Max.CPUclock rate | 400 MHz to 5.3 GHz |
| FSB speeds | 100 MT/s to 1.6 GT/s |
| QPI speeds | 4.8 GT/s to 24 GT/s |
| DMI speeds | 2.0 GT/s to 16 GT/s |
| Data width | Up to 64 bits |
| Address width | Up to 64 bits |
| Virtual address width | Up to 57 bits |
| Cache | |
| L1cache | Up to 80 KB per core |
| L2 cache | Up to 2 MB per core |
| L3 cache | Up to 320 MB per socket |
| L4 cache | Up to 64 GBHBM2e[2] |
| Architecture and classification | |
| Application | |
| Technology node | 250 nm to Intel 3 and TSMC N5 |
| Microarchitecture | |
| Instruction set | x86-16,IA-32,x86-64 |
| Instructions | MMX,SSE,SSE2,SSE3,SSSE3,SSE4,SSE4.1,SSE4.2,AVX,AVX2,FMA3,AVX-512,AVX-VNNI,AMX,TSX,AES-NI,CLMUL,RDRAND |
| Extensions | |
| Physical specifications | |
| Cores |
|
| Memory (RAM) | |
| GPU | Intel Graphics Technology (some models only) |
| Co-processor | Xeon Phi (2010–2020) |
| Socket | |
| Products, models, variants | |
| Brand name | |
| Variant |
|
| History | |
| Predecessor | Pentium Pro |
| Support status | |
| Supported | |
Xeon (/ˈziːɒn/;ZEE-on) is a brand ofx86microprocessors designed, manufactured, and marketed byIntel, targeted at the non-consumerworkstation,server, andembedded markets. It was introduced in June 29, 1998.[1] Xeon processors are based on the same architecture as regular desktop-grade CPUs, but have advanced features such as support forerror correction code (ECC) memory, highercore counts, morePCI Express lanes, support for larger amounts of RAM, largercache memory and extra provision for enterprise-gradereliability, availability and serviceability (RAS) features responsible for handling hardware exceptions through theMachine Check Architecture (MCA). They are often capable of safely continuing execution where a normal processor cannot due to these extra RAS features, depending on the type and severity of themachine-check exception (MCE). Some also support multi-socket systems with two, four, or eight sockets through use of theUltra Path Interconnect (UPI) bus, which replaced the olderQuickPath Interconnect (QPI) bus.
TheXeon brand has been maintained over several generations ofIA-32 andx86-64 processors. The P6-based models added theXeon moniker to the end of the name of their corresponding desktop processor, but all models since 2001 used the nameXeon on its own. TheXeon CPUs generally have morecache andcores than their desktop counterparts in addition to multiprocessing capabilities.
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The Xeon Scalable brand for high-performance server was introduced in May 2017 with the Skylake-based Xeon Platinum 8100 series. Xeon Scalable processors range from dual socket to 8 socket support. Within the Xeon Scalable brand, there exists the hierarchy of Xeon Bronze, Silver, Gold and Platinum.
In April 2024, Intel announced at its Vision event that the Xeon Scalable brand would be retired, beginning with 6th generation Xeon processors codenamedSierra Forest andGranite Rapids that will now be referred to as "Xeon 6" processors.[5] This change brings greater emphasis on processor generation numbers.[6]
With the launch of Intel'sSierra Forest line of processors, branding for mainstream server processors switched to Xeon #, with the # being the generation of the processor, such as Xeon 6 for the 6th generation of Xeon processors, this naming convention also carries over to the Granite Rapids line of server CPUs.[7]
Xeon 6 is split into two product lines, the E series and P series, which, respectively, are all E core and all P core designs. For example, the Xeon 6 6700E line is an allE core based (Sierra Forest) line of processors.[7]
Xeon D is targeted towards microserver and edge computing markets with lower power consumption and integrated I/O blocks such asnetwork interface controllers. This allows Xeon D processors to function as SoCs that do not require a separate southbridge PCH.[8] It was announced in 2014 and the first Xeon D processors were released in March 2015. Xeon D processors come in ansolderedBGA package rather than in a socketable form factor. Xeon D was introduced to compete with emerging ARM hyperscale server solutions that offered greater multi-threaded performance and power effiency.[9]
Early 2025, theXeon 6 SoC line was announced as the 'next gen' for at least a part of the Xeon D lineup.[10]
Xeon W branding is used for Xeon workstation processors. It was first introduced in August 2017 with the release of theSkylake-based Xeon W-2100 series workstation processors. With Sapphire Rapids-WS workstation processors that launched in March 2023, Intel introduced tiers within Xeon W. Xeon w3, w5, w7 and w9 was designed to emulate the Core i3, i5, i7 and i9 branding that Intel had been using for its desktop processors.
Some shortcomings that make Xeon processors unsuitable for most consumer-grade desktop PCs include lowerclock rates at the same price point (since servers run more tasks in parallel than desktops, core counts are more important than clock rates), and, usually, the lack of an integratedgraphics processing unit (GPU). Processor models prior toSapphire Rapids-WS lack support foroverclocking (with the exception ofXeon W-3175X). Despite such disadvantages, Xeon processors have always had popularity among some desktop users (video editors and otherpower users), mainly due to higher core count potential, and higher performance to price ratio vs. theCore i7 in terms of total computing power of all cores. Since most Intel Xeon CPUs lack an integratedGPU, systems built with those processors require a discrete graphics card or a separate GPU ifcomputer monitor output is desired.
Intel Xeon is a distinct product line from the similarly named IntelXeon Phi. The first-generation Xeon Phi is a completely different type of device more comparable to a graphics card; it is designed for aPCI Express slot and is meant to be used as a multi-core coprocessor, like theNvidia Tesla. In the second generation, Xeon Phi evolved into a main processor more similar to the Xeon. It conforms to the same socket as a Xeon processor and is x86-compatible; however, as compared to Xeon, the design point of the Xeon Phi emphasizes more cores with higher memory bandwidth.
| 1 or 2 Sockets UP/DP/3000/5000/E3/E5-1xxx and 2xxx/E7-2xxx/D/E/W series Bronze/Silver/Gold (non H)/Platinum (non H)/Max | 4 or 8 Sockets MP/7000/E5-4xxx/E7-4xxx and 8xxx seriesGold (H)/Platinum (H) | |||||
|---|---|---|---|---|---|---|
Node | Code named | # of Cores | Release date | Code named | # of Cores | Release date |
250 nm | Drake | 1 | Jun 1998 | |||
| Tanner | 1 | Mar 1999 | ||||
180 nm | Cascades (256 KB L2 cache) | 1 | Oct 1999 | Cascades (700 and 900 MHz models only) | 1 | May 2000 |
| Foster | 1 | May 2001 | Foster MP | 1 | Mar 2002 | |
130 nm | Prestonia | 1 | Feb 2002 | |||
| Gallatin DP | 1 | Jul 2003 | Gallatin | 1 | Nov 2002 | |
90 nm | Nocona | 1 | Jun 2004 | Cranford | 1 | Mar 2005 |
| Potomac | 1 | Mar 2005 | ||||
| Irwindale | 1 | Feb 2005 | ||||
| Paxville DP | 2 | Oct 2005 | Paxville | 2 | Nov 2005 | |
65 nm | Dempsey | 2 | May 2006 | Tulsa | 2 | Aug 2006 |
| Sossaman | 2 | Mar 2006 | ||||
| Woodcrest | 2 | Jun 2006 | ||||
| Conroe | 2 | Oct 2006 | ||||
| Clovertown | 4 | Nov 2006 | Tigerton/Tigerton QC | 2/4 | Sep 2007 | |
| Allendale | 2 | Jan 2007 | ||||
| Kentsfield | 4 | Jan 2007 | ||||
45 nm | Wolfdale DP | 2 | Nov 2007 | |||
| Harpertown | 4 | Nov 2007 | Dunnington QC/Dunnington | 4/6 | Sep 2008 | |
| Wolfdale | 2 | Feb 2008 | ||||
| Yorkfield | 4 | Mar 2008 | ||||
| Bloomfield (W35xx) | 4 | Mar 2009 | ||||
| Gainestown (55xx) | 2/4 | Mar 2009 | ||||
| Lynnfield (34xx) | 4 | Sep 2009 | ||||
| Beckton (65xx) | 4/6/8 | Mar 2010 | Beckton (75xx) | 4-8 | Mar 2010 | |
32 nm | Westmere-EP (56xx) | 2-6 | Mar 2010 | |||
| Gulftown (W36xx) | 6 | Mar 2010 | ||||
| Clarkdale (L34xx) | 2 | Mar 2010 | ||||
| Westmere-EX (E7-2xxx) | 6-10 | Apr 2011 | Westmere-EX (E7-4xxx/8xxx) | 6-10 | Apr 2011 | |
| Sandy Bridge-DT/EN/EP | 2-8 | Mar 2012 | Sandy Bridge-EP (E5-46xx) | 4-8 | May 2012 | |
22 nm | Ivy Bridge (E3/E5-1xxx/E5-2xxx v2) | 2-12 | Sep 2013 | Ivy Bridge-EP (E5-46xx v2) | 4-12 | Mar 2014 |
| Ivy Bridge-EX (E7-28xx v2) | 12/15 | Feb 2014 | Ivy Bridge-EX (E7-48xx/88xx v2) | 6-12/15 | Feb 2014 | |
| Haswell (E3/E5-1xxx/E5-2xxx v3) | 2-18 | Sep 2014 | Haswell-EP (E5-46xx v3) | 6-18 | Jun 2015 | |
| Haswell-EX (E7-48xx/88xx v3) | 4-18 | May 2015 | ||||
14 nm | Broadwell (E3/E5-1xxx/E5-2xxx v4) | 4-22 | Jun 2015 | |||
| Skylake-S/H (E3-1xxx v5) | 4 | Oct 2015 | ||||
| Kaby Lake-S/H (E3-1xxx v6) | 4 | Mar 2017 | ||||
| Skylake-W/SP (Bronze and Silver) | 4-28 | Jun 2017 | Skylake-SP (Gold and Platinum) | 4-28 | Jul 2017 | |
| Cascade Lake-W/SP (Bronze/Silver/R/U) | 4-28 | Apr 2019 | Cascade Lake-SP (Gold (non-R/U)/Platinum) | 4-28 | Apr 2019 | |
| Cooper Lake-SP | 8-28 | Jun 2020 | ||||
10 nm | Ice Lake-SP/W | 8-40 | Apr 2021 | |||
| Ice Lake-D | 2-20 | Feb 2022 | ||||
Intel 7 | Sapphire Rapids-SP/WS/HBM | 6-56 | Jan 2023 | Sapphire Rapids-SP | 8-60 | Jan 2023 |
| Emerald Rapids-SP | 8-64 | Dec 2023 | ||||
| List of Intel Xeon processors | ||||||
The first Xeon-branded processor was the Pentium II Xeon (code-named "Drake"). It was released in 1998, replacing thePentium Pro in Intel's high-end server lineup. The Pentium II Xeon was a "Deschutes"Pentium II (and shared the same product code: 80523) with a full-speed 512 kB (1 kB = 1024 B), 1 MB (1 MB = 1024 kB = 10242 B), or 2 MBL2 cache. The L2 cache was implemented with custom 512 kB SRAMs developed by Intel. The number of SRAMs depended on the amount of cache. A 512 kB configuration required one SRAM, a 1 MB configuration: two SRAMs, and a 2 MB configuration: four SRAMs on both sides of the PCB. Each SRAM was a 12.90 mm by 17.23 mm (222.21 mm2) die fabricated in a 0.35 μm four-layer metal CMOS process and packaged in a cavity-down wire-bondedland grid array (LGA).[11] The additional cache required a larger module and thus the Pentium II Xeon used a larger slot,Slot 2. It was supported by thei440GX dual-processor workstationchipset and thei450NX quad- or octo-processor server chipset.
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In 1999, thePentium II Xeon was replaced by thePentium III Xeon. Reflecting the incremental changes from the Pentium II "Deschutes" core to the Pentium III "Katmai" core, the first Pentium III Xeon, named "Tanner", was just like its predecessor except for the addition ofStreaming SIMD Extensions (SSE) and a few cache controller improvements. The product codes forTanner mirrored that ofKatmai; 80525.
The second version, named "Cascades", was based on the Pentium III "Coppermine" core. The "Cascades" Xeon used a 133 MT/s front side bus and relatively small 256 kB on-die L2 cache resulting in almost the same capabilities as theSlot 1Coppermine processors, which were capable of dual-processor operation but not quad-processor or octa-processor operation.
To improve this situation, Intel released another version, officially also named "Cascades", but often referred to as "Cascades 2 MB". That came in two variants: with 1 MB or 2 MB of L2 cache. Its bus speed was fixed at 100 MT/s, though in practice the cache was able to offset this. The product code forCascades mirrored that ofCoppermine; 80526.
In mid-2001, the Xeon brand was introduced ("Pentium" was dropped from the name). The initial variant that used the newNetBurst microarchitecture, "Foster", was slightly different from the desktopPentium 4 ("Willamette"). It was a decent[clarification needed] chip for workstations, but for server applications it was almost always outperformed by the older Cascades cores with a 2 MB L2 cache and AMD'sAthlon MP[example needed]. Combined with the need to use expensiveRambus Dynamic RAM, the Foster's sales were somewhat unimpressive[example needed].
At most two Foster processors could be accommodated in asymmetric multiprocessing (SMP) system built with a mainstream chipset, so a second version (Foster MP) was introduced with 512 KB or 1 MB L3 cache and the JacksonHyper-Threading capacity. This improved performance slightly, but not enough to lift it out of third place. It was also priced much higher than the dual-processor (DP) versions. TheFoster shared the 80528 product code with Willamette.
In 2002, Intel released a130 nm version of Xeon branded CPU, codenamed "Prestonia". It supported Intel's new Hyper-Threading technology and had a 512 kB L2 cache. This was based on the "Northwood" Pentium 4 core. A new server chipset,E7500 (which allowed the use of dual-channelDDR SDRAM), was released to support this processor in servers, and soon the bus speed was boosted to 533 MT/s (accompanied by a new socket and two new chipsets: the E7501 for servers and the E7505 for workstations). ThePrestonia performed much better than its predecessor and noticeably better than Athlon MP. The support of new features in the E75xx series also gave it a key advantage over the Pentium III Xeon and Athlon MP branded CPUs (both stuck with rather old chipsets), and it quickly became the top-selling server/workstation processor.
%2c_Socket_604.jpg) | |
| General information | |
|---|---|
| Launched | March 2003 |
| Discontinued | 2004 |
| CPUID code | 0F7x |
| Product code | 80537 |
| Performance | |
| Max.CPUclock rate | 1.50 GHz to 3.20 GHz |
| FSB speeds | 400 MT/s to 533 MT/s |
| Cache | |
| L1cache | 8 kB + 12 kuOps trace cache |
| L2 cache | 512 kB |
| L3 cache | 1 MB, 2 MB, 4 MB |
| Architecture and classification | |
| Application | DP and MP Server |
| Technology node | 130 nm |
| Microarchitecture | NetBurst |
| Instruction set | x86-16,IA-32 |
| Physical specifications | |
| Cores |
|
| Package | |
| Products, models, variants | |
| Brand name |
|
Subsequent to thePrestonia was the "Gallatin", which had an L3 cache of 1 MB or 2 MB. Its Xeon MP version, which succeededFoster MP, was popular in servers. Later experience with the 130 nm process allowed Intel to create the Xeon MP brandedGallatin with 4 MB cache. The Xeon brandedPrestonia andGallatin were designated 80532, like Northwood.
Due to a lack of success with Intel'sItanium and Itanium 2 processors, AMD was able to introducex86-64, a 64-bit extension to thex86 architecture. Intel followed suit by includingIntel 64 (formerly EM64T; it is almost identical toAMD64) in the90 nm version of the Pentium 4 ("Prescott"), and a Xeon version codenamed "Nocona" with 1 MB L2 cache was released in 2004. Released with it were the E7525 (workstation), E7520 and E7320 (both server) chipsets, which added support forPCI Express 1.0a,DDR2 andSerial ATA 1.0a. The Xeon was noticeably slower than AMD's Opteron, although it could be faster in situations where Hyper-Threading came into play.
A slightly updated core called "Irwindale" was released in early 2005, with 2 MB L2 cache and the ability to have its clock speed reduced during low processor demand. Although it was a bit more competitive than theNocona had been, independenttests showed that AMD's Opteron still outperformedIrwindale. Both of these Prescott-derived Xeons have the product code 80546.
64-bit Xeon MPs were introduced in April 2005. The cheaper "Cranford" was an MP version ofNocona, while the more expensive "Potomac" was aCranford with 8 MB of L3 cache. Like Nocona and Irwindale, they also have product code 80546.
| General information | |
|---|---|
| Launched | October 2005 |
| Discontinued | August 2008 |
| CPUID code | 0F48 |
| Product code | 80551, 80560 |
| Performance | |
| Max.CPUclock rate | 2.667 GHz to 3.0 GHz |
| FSB speeds | 667 MT/s to 800 MT/s |
| Cache | |
| L2 cache | 2×2 MB |
| Architecture and classification | |
| Application | DP Server, MP Server |
| Technology node | 90 nm |
| Microarchitecture | NetBurst |
| Instruction set | x86-16,IA-32,x86-64 |
| Physical specifications | |
| Cores |
|
| Package | |
| Products, models, variants | |
| Brand name |
|
The firstdual-core CPU branded Xeon, codenamedPaxville DP, product code 80551, was released by Intel on October 10, 2005. Paxville DP hadNetBurst microarchitecture, and was a dual-core equivalent of the single-coreIrwindale (related to thePentium D branded "Smithfield") with 4 MB of L2 cache (2 MB per core). The only Paxville DP model released ran at 2.8 GHz, featured an 800 MT/s front side bus, and was produced using a90 nm process.
An MP-capable version of Paxville, codenamedPaxville MP, product code 80560, was released on November 1, 2005. There are two versions: one with 2 MB of L2 cache (1 MB per core), and one with 4 MB of L2 (2 MB per core). Paxville MP, called the dual-core Xeon 7000-series, was produced using a 90 nm process. Paxville MP clock ranges between 2.67 GHz and 3.0 GHz (model numbers 7020–7041), with some models having a 667 MT/s FSB, and others having an 800 MT/s FSB.
| Model | Speed | L2 cache | FSB | TDP |
|---|---|---|---|---|
| 7020 | 2.66 GHz | 2 × 1 MB | 667 MT/s | 165 W |
| 7030 | 2.80 GHz | 800 MT/s | ||
| 7040 | 3.00 GHz | 2 × 2 MB | 667 MT/s | |
| 7041 | 800 MT/s |
| General information | |
|---|---|
| Launched | August 2006 |
| Discontinued | August 2008 |
| CPUID code | 0F68 |
| Product code | 80550 |
| Performance | |
| Max.CPUclock rate | 2.50 GHz to 3.50 GHz |
| FSB speeds | 667 MT/s to 800 MT/s |
| Cache | |
| L2 cache | 2×1 MB |
| L3 cache | 16 MB |
| Architecture and classification | |
| Application | MP Server |
| Technology node | 65 nm |
| Microarchitecture | NetBurst |
| Instruction set | x86-16,IA-32,x86-64 |
| Physical specifications | |
| Cores |
|
| Package | |
| Products, models, variants | |
| Brand name |
|
Released on August 29, 2006,[12] the 7100 series, codenamedTulsa (product code 80550), is an improved version of Paxville MP, built on a 65 nm process, with 2 MB of L2 cache (1 MB per core) and up to 16 MB of L3 cache. It usesSocket 604.[13] Tulsa was released in two lines: the N-line uses a 667 MT/s FSB, and the M-line uses an 800 MT/s FSB. The N-line ranges from 2.5 GHz to 3.5 GHz (model numbers 7110N-7150N), and the M-line ranges from 2.6 GHz to 3.4 GHz (model numbers 7110M-7140M). L3 cache ranges from 4 MB to 16 MB across the models.[14]
| Model | Speed | L2 cache | L3 cache | FSB | TDP |
|---|---|---|---|---|---|
| 7110N | 2.50 GHz | 2 MB | 4 MB | 667 MT/s | 95 W |
| 7110M | 2.60 GHz | 800 MT/s | |||
| 7120N | 3.00 GHz | 667 MT/s | |||
| 7120M | 800 MT/s | ||||
| 7130N | 3.16 GHz | 8 MB | 667 MT/s | 150 W | |
| 7130M | 3.20 GHz | 800 MT/s | |||
| 7140N | 3.33 GHz | 16 MB | 667 MT/s | ||
| 7140M | 3.40 GHz | 800 MT/s | |||
| 7150N | 3.50 GHz | 667 MT/s |
| General information | |
|---|---|
| Launched | May 2006 |
| Discontinued | August 2008 |
| Performance | |
| Max.CPUclock rate | 2.50 GHz to 3.73 GHz |
| FSB speeds | 667 MT/s to 1066 MT/s |
| Cache | |
| L2 cache | 4 MB |
| Architecture and classification | |
| Application | DP Server |
| Technology node | 65nm |
| Microarchitecture | NetBurst |
| Instruction set | x86-16,IA-32,x86-64 |
| Physical specifications | |
| Cores |
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| Package | |
| Products, models, variants | |
| Brand name |
|
On May 23, 2006, Intel released the dual-core CPU (Xeon branded 5000 series) codenamedDempsey (product code 80555). Released as the Dual-Core Xeon 5000-series, Dempsey is aNetBurst microarchitecture processor produced using a65 nm process, and is virtually identical to Intel's "Presler"Pentium Extreme Edition, except for the addition of SMP support, which lets Dempsey operate in dual-processor systems. Dempsey ranges between 2.50 GHz and 3.73 GHz (model numbers 5020–5080). Some models have a 667 MT/s FSB, and others have a 1066 MT/s FSB. Dempsey has 4 MB of L2 cache (2 MB per core). A Medium Voltage model, at 3.2 GHz and 1066 MT/s FSB (model number 5063), has also been released. Dempsey also introduces a new interface for Xeon processors:LGA 771, also known asSocket J. Dempsey was the first Xeon core in a long time to be somewhat competitive with its Opteron-based counterparts, although it could not claim a decisive lead in any performance metric – that would have to wait for its successor, the Woodcrest.
| Model | Speed (GHz) | L2 cache | FSB | TDP |
|---|---|---|---|---|
| 5020 | 2.50 GHz | 2 × 2 MB | 667 MT/s | 95 W |
| 5030 | 2.66 GHz | |||
| 5040 | 2.83 GHz | |||
| 5050 | 3.00 GHz | |||
| 5060 | 3.20 GHz | 1.07 GT/s | 130 W | |
| 5063 | 95 W | |||
| 5070 | 3.46 GHz | 130 W | ||
| 5080 | 3.73 GHz |
 | |
| General information | |
|---|---|
| Launched | 2006 |
| Discontinued | 2008 |
| CPUID code | 06Ex |
| Product code | 80539 |
| Performance | |
| Max.CPUclock rate | 1.667 GHz to 2.167 GHz |
| FSB speeds | 667 MT/s |
| Cache | |
| L2 cache | 2 MB |
| Architecture and classification | |
| Application | DP Server |
| Technology node | 65 nm |
| Microarchitecture | Enhanced Pentium M |
| Instruction set | x86-16,IA-32 |
| Physical specifications | |
| Cores |
|
| Package | |
| Products, models, variants | |
| Brand name |
|
On March 14, 2006, Intel released a dual-core processor codenamedSossaman and branded asXeon LV (low-voltage). Subsequently, an ULV (ultra-low-voltage) version was released. TheSossaman was a low-/ultra-low-power and double-processor capable CPU (likeAMD Quad FX), based on the "Yonah" processor, for ultradense non-consumer environment (i.e., targeted at the blade-server and embedded markets), and was rated at athermal design power (TDP) of 31 W (LV: 1.66 GHz, 2 GHz and 2.16 GHz) and 15 W (ULV: 1.66 GHz).[15] As such, it supported most of the same features as earlier Xeons: Virtualization Technology, 667 MT/s front side bus, and dual-core processing, but did not support 64-bit operations, so it could not run 64-bit server software, such asMicrosoft Exchange Server 2007, and therefore was limited to 16 GB of memory. A planned successor, codenamed "Merom MP" was to be a drop-in upgrade to enableSossaman-based servers to upgrade to 64-bit capability. However, this was abandoned in favor of low-voltage versions of theWoodcrest LV processor leaving theSossaman at a dead-end with no upgrade path.
| Model | Speed | L2 cache | FSB | TDP |
|---|---|---|---|---|
| ULV 1.66 | 1.66 GHz | 2 MB | 667 MT/s | 15 W |
| LV 1.66 | 31 W | |||
| LV 2.00 | 2.00 GHz | |||
| LV 2.16 | 2.16 GHz |
The 3000 series, codenamedConroe (product code 80557) dual-core Xeon (branded) CPU,[16] released at the end of September 2006, was the first Xeon for single-CPU operation and is designed for entry-level uniprocessor servers. The same processor is branded asCore 2 Duo or asPentium Dual-Core andCeleron, with varying features disabled. They useLGA 775 (Socket T), operate on a 1066 MT/s front-side bus, support Enhanced IntelSpeedStep Technology and Intel Virtualization Technology but do not support hyper-threading. Conroe processors with a number ending in "5" have a 1333 MT/s FSB.[17]
| Model | Speed | L2 cache | FSB | TDP |
|---|---|---|---|---|
| 3040 | 1.86 GHz | 2 MB | 1066 MT/s | 65 W |
| 3050 | 2.13 GHz | |||
| 3055* | 4 MB | |||
| 3060 | 2.4 GHz | |||
| 3065 | 2.33 GHz | 1333 MT/s | ||
| 3070 | 2.66 GHz | 1066 MT/s | ||
| 3075 | 1333 MT/s | |||
| 3080* | 2.93 GHz | 1066 MT/s | ||
| 3085 | 3.00 GHz | 1333 MT/s |
The 3100 series, codenamedWolfdale (product code 80570) dual-core Xeon (branded) CPU, was just a rebranded version of the Intel's mainstreamCore 2 Duo E7000/E8000 andPentium Dual-Core E5000 processors, featuring the same45 nm process and 6 MB of L2 cache. Unlike most Xeon processors, they only support single-CPU operation. They useLGA 775 (Socket T), operate on a 1333 MT/s front-side bus, support Enhanced IntelSpeedStep Technology and Intel Virtualization Technology but do not support Hyper-Threading.
| Model | Speed | L2 cache | FSB | TDP |
|---|---|---|---|---|
| E3110 | 3.00 GHz | 6 MB | 1333 MT/s | 65 W |
| L3110 | 45 W | |||
| E3120 | 3.16 GHz | 65 W |
 | |
| General information | |
|---|---|
| Launched | 2006; 19 years ago (2006) |
| Discontinued | 2009; 16 years ago (2009) |
| Marketed by | Intel |
| Designed by | Intel |
| Common manufacturer |
|
| CPUID code | 06Fx |
| Product code | 80556 |
| Performance | |
| Max.CPUclock rate | 1.60 GHz to 3.0 GHz |
| FSB speeds | 1066 MT/s to 1333 MT/s |
| Cache | |
| L1cache | 128 KB (64 KB (32 KB instruction + 32 KB data) x 2) |
| L2 cache | 4 MB |
| Architecture and classification | |
| Application | DP Server |
| Technology node | 65nm |
| Microarchitecture | Core/Merom |
| Instruction set | x86-16,IA-32,x86-64 |
| Physical specifications | |
| Cores |
|
| Socket | |
| Products, models, variants | |
| Brand name |
|
| Variants |
|
| History | |
| Predecessor | Dempsey |
| Successor | Wolfdale-DP |
On June 26, 2006, Intel released the dual-core CPU (Xeon branded 5100 series) codenamedWoodcrest (product code 80556); it was the first IntelCore/Merom microarchitecture processor to be launched on the market. It is a dual-processor server and workstation version of theCore 2 processor. Intel claimed that it provides an 80% boost in performance, while reducing power consumption by 20% relative to the 5000 seriesDempsey.
Most models have a 1333 MT/s FSB, except for the 5110 and 5120, which have a 1066 MT/s FSB. The fastest processor (5160) operates at 3.0 GHz. All Woodcrest processors use theLGA 771 (Socket J) socket and all except two models have a TDP of 65 W. The 5160 has a TDP of 80 W and the 5148LV (2.33 GHz) has a TDP of 40 W. The previous generation Xeons had a TDP of 130 W. All models support Intel 64 (Intel's x86-64 implementation), theXD bit, andVirtualization Technology, with theDemand-based switching power management option only on Dual-Core Xeon 5140 or above. Woodcrest has 4 MB of shared L2 cache.
| Model | Speed | L2 cache | FSB | TDP |
|---|---|---|---|---|
| 5110 | 1.60 GHz | 4 MB | 1066 MT/s | 65 W |
| 5120 | 1.83 GHz | |||
| 5128 | 40 W | |||
| 5130 | 2.0 GHz | 1333 MT/s | 65 W | |
| 5138 | 2.13 GHz | 1066 MT/s | 35 W | |
| 5140 | 2.33 GHz | 1333 MT/s | 65 W | |
| 5148 | 40 W | |||
| 5150 | 2.66 GHz | 65 W | ||
| 5160 | 3.00 GHz | 80 W |
| General information | |
|---|---|
| Launched | 2007 |
| Discontinued | present |
| CPUID code | 1067x |
| Product code | 80573 |
| Performance | |
| Max.CPUclock rate | 1.866 GHz to 3.50 GHz |
| FSB speeds | 1066 MT/s to 1600 MT/s |
| Cache | |
| L2 cache | 6 MB |
| Architecture and classification | |
| Application | DP Server |
| Technology node | 45 nm |
| Microarchitecture | Penryn |
| Instruction set | x86-16,IA-32,x86-64 |
| Physical specifications | |
| Cores |
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| Package | |
| Products, models, variants | |
| Brand name |
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On November 11, 2007, Intel released the dual-core CPU (Xeon branded 5200 series) codenamedWolfdale-DP (product code 80573).[19] It is built on a45 nm process like the desktop Core 2 Duo and XeonWolfdale, featuring Intel 64 (Intel's x86-64 implementation), theXD bit, andVirtualization Technology. It is unclear whether theDemand-based switching power management is available on the L5238.[20] Wolfdale has 6 MB of shared L2 cache.
| Model | Speed (GHz) | L2 cache | FSB | TDP |
|---|---|---|---|---|
| E5205 | 1.86 GHz | 6 MB | 1066 MT/s | 65 W |
| L5238 | 2.66 GHz | 1333 MT/s | 35 W | |
| L5240 | 3.00 GHz | 40 W | ||
| X5260 | 3.33 GHz | 80 W | ||
| X5270 | 3.50 GHz | |||
| X5272 | 3.40 GHz | 1600 MT/s |
The 7200 series, codenamedTigerton (product code 80564) is an MP-capable processor, similar to the7300 series, but, in contrast, there is a single dual-core die.[21][22][23][24]
| Model | Speed | L2 cache | FSB | TDP |
|---|---|---|---|---|
| E7210 | 2.40 GHz | 4 MB | 1066 MT/s | 80 W |
| E7220 | 2.93 GHz |
Intel released rebranded versions of its quad-core (2×2) Core 2 Quad processor as the Xeon 3200-series (product code 80562) on January 7, 2007.[25] The 2 × 2 "quad-core" (dual-die dual-core[26]) comprised two separate dual-core die next to each other in one CPU package. The models are the X3210, X3220 and X3230, running at 2.13 GHz, 2.4 GHz and 2.66 GHz, respectively.[27] Like the 3000-series, these models only support single-CPU operation and operate on a 1066 MT/s front-side bus. It is targeted at the "blade" market. The X3220 is also branded and sold asCore2 Quad Q6600, the X3230 as Q6700.
| Model | Speed | L2 cache | FSB | TDP |
|---|---|---|---|---|
| X3210 | 2.13 GHz | 4 MB × 2 | 1066 MT/s | 100/105 W |
| X3220 | 2.40 GHz | |||
| X3230 | 2.66 GHz | 100 W |
Intel released relabeled versions of its quad-coreCore 2 Quad Yorkfield Q9300, Q9400, Q9x50 and QX9770 processors as the Xeon 3300-series (product code 80569). This processor comprises two separate dual-core dies next to each other in one CPU package and manufactured in a45 nm process. The models are the X3320, X3330, X3350, X3360, X3370 and X3380, being rebadged Q9300, Q9400, Q9450, Q9550, Q9650, QX9770, running at 2.50 GHz, 2.66 GHz, 2.66 GHz, 2.83 GHz, 3.0 GHz, and 3.16 GHz, respectively. The L2 cache is a unified 6 MB per die (except for the X3320 and X3330 with a smaller 3 MB L2 cache per die), and a front-side bus of 1333 MHz. All models feature Intel 64 (Intel's x86-64 implementation), theXD bit, andVirtualization Technology, as well asDemand-based switching.
TheYorkfield-CL (product code 80584) variant of these processors are X3323, X3353 and X3363. They have a reduced TDP of 80W and are made for single-CPULGA 771 systems instead ofLGA 775, which is used in all other Yorkfield processors. In all other respects, they are identical to their Yorkfield counterparts.
 | |
| General information | |
|---|---|
| Launched | 2006 |
| Discontinued | present |
| CPUID code | 06Fx |
| Product code | 80563 |
| Performance | |
| Max.CPUclock rate | 1.60 GHz to 3.0 GHz |
| FSB speeds | 1066 MT/s to 1333 |
| Cache | |
| L2 cache | 2×4 MB |
| Architecture and classification | |
| Application | DP Server |
| Technology node | 65 nm |
| Microarchitecture | Core |
| Instruction set | x86-16,IA-32,x86-64 |
| Physical specifications | |
| Cores |
|
| Package | |
| Products, models, variants | |
| Brand name |
|
A quad-core (2×2) successor of the Woodcrest for DP segment, consisting of two dual-core Woodcrest chips in one package similarly to the dual-core Pentium D branded CPUs (two single-core chips) or the quad-coreKentsfield. All Clovertowns use theLGA 771 package. The Clovertown has been usually implemented with two Woodcrest dies on amulti-chip module, with 8 MB of L2 cache (4 MB per die). Like Woodcrest, lower models use a 1066 MT/s FSB, and higher models use a 1333 MT/s FSB. Intel releasedClovertown, product code 80563, on November 14, 2006[28] with models E5310, E5320, E5335, E5345, and X5355, ranging from 1.6 GHz to 2.66 GHz. All models support MMX, SSE, SSE2, SSE3, SSSE3, Intel 64, XD bit (an NX bit implementation),Intel VT. The E and X designations are borrowed from Intel's Core 2 model numbering scheme; an ending of -0 implies a 1066 MT/s FSB, and an ending of -5 implies a 1333 MT/s FSB.[27] All models have a TDP of 80 W with the exception of the X5355, which has a TDP of 120 W, and the X5365, which has a TDP of 150 W. A low-voltage version of Clovertown with a TDP of 50 W has a model numbers L5310, L5320 and L5335 (1.6 GHz, 1.86 GHz and 2.0 GHz respectively). The 3.0 GHz X5365 arrived in July 2007, and became available in theAppleMac Pro[29] on April 4, 2007.[30][31] The X5365 performs up to around 38 GFLOPS in the LINPACK benchmark.[32]
| Model | Speed | L2 cache | FSB | TDP |
|---|---|---|---|---|
| E5310 | 1.60 GHz | 4 MB × 2 | 1066 MT/s | 80 W |
| L5310 | 50 W | |||
| E5320 | 1.86 GHz | 80 W | ||
| L5320 | 50 W | |||
| E5335 | 2.00 GHz | 1333 MT/s | 80 W | |
| L5335 | 50 W | |||
| E5345 | 2.33 GHz | 80 W | ||
| X5355 | 2.66 GHz | 120 W | ||
| X5365 | 3.00 GHz | 150 W |
| General information | |
|---|---|
| Launched | 2007 |
| Discontinued | present |
| CPUID code | 1067x |
| Product code | 80574 |
| Performance | |
| Max.CPUclock rate | 2.0 GHz to 3.40 GHz |
| FSB speeds | 1066 MT/s to 1600 |
| Cache | |
| L2 cache | 2 × 6 MB |
| Architecture and classification | |
| Application | DP Server |
| Technology node | 45 nm |
| Microarchitecture | Penryn |
| Instruction set | x86-16,IA-32,x86-64 |
| Physical specifications | |
| Cores |
|
| Package | |
| Products, models, variants | |
| Brand names |
|
On November 11, 2007 Intel presentedYorkfield-based Xeons – called Harpertown (product code 80574) – to the public.[33] This family consists of dual die quad-core CPUs manufactured on a45 nm process and featuring 1066 MHz, 1333 MHz, 1600 MHz front-side buses, with TDP rated from 40 W to 150 W depending on the model. These processors fit in theLGA 771 package. All models feature Intel 64 (Intel's x86-64 implementation), theXD bit, andVirtualization Technology. All except the E5405 and L5408 also featureDemand-based switching. The supplementary character in front of the model-number represents the thermal rating: an L depicts a TDP of 40 W or 50 W, an E depicts 80 W whereas an X is 120 W TDP or above. The speed of 3.00 GHz comes as four models, two models with 80 W TDP two other models with 120 W TDP with 1333 MHz or 1600 MHz front-side bus respectively. The fastest Harpertown is the X5492 whose TDP of 150 W is higher than those of the Prescott-based Xeon DP but having twice as many cores. (The X5482 is also sold under the name "Core 2 Extreme QX9775" for use in theIntel Skulltrail system.)
Intel 1.6 GT/s front-side bus Xeon processors will drop into the Intel 5400 (Seaburg) chipset whereas several mainboards featuring the Intel 5000/5200-chipset are enabled to run the processors with a 1333 MHz front-side bus speed. Seaburg features support for dualPCIe 2.0 x16 slots and up to 128 GB of memory.[34][35]
| Model | Speed | L2 cache | FSB | TDP |
|---|---|---|---|---|
| E5405 | 2.00 GHz | 2 × 6 MB | 1333 MT/s | 80 W |
| L5408 | 2.13 GHz | 1066 MT/s | 40 W | |
| E5410 | 2.33 GHz | 1333 MT/s | 80 W | |
| L5410 | 50 W | |||
| E5420 | 2.50 GHz | 80 W | ||
| L5420 | 50 W | |||
| E5430 | 2.66 GHz | 80 W | ||
| L5430 | 50 W | |||
| E5440 | 2.83 GHz | 80 W | ||
| X5450 | 3.00 GHz | 120 W | ||
| E5450 | 80 W | |||
| X5460 | 3.16 GHz | 120 W | ||
| X5470 | 3.33 GHz | |||
| E5462 | 2.80 GHz | 1600 MT/s | 80 W | |
| E5472 | 3.00 GHz | |||
| X5472 | 120 W | |||
| X5482 | 3.20 GHz | 150 W | ||
| X5492 | 3.40 GHz |
| General information | |
|---|---|
| Launched | 2007 |
| Discontinued | present |
| CPUID code | 06Fx |
| Product code | 80564 80565 |
| Performance | |
| Max.CPUclock rate | 1.60 GHz to 2.933 GHz |
| FSB speeds | 1066 MT/s |
| Cache | |
| L2 cache | 2×2 or 2×4 MB |
| Architecture and classification | |
| Application | MP Server |
| Technology node | 65 nm |
| Microarchitecture | Core |
| Instruction set | x86-16,IA-32,x86-64 |
| Physical specifications | |
| Cores |
|
| Package | |
| Products, models, variants | |
| Brand names |
|
The 7300 series, codenamedTigerton QC (product code 80565) is a four-socket (packaged inSocket 604) and more capablequad-core processor, consisting of twodual core Core 2 architecture silicon chips on a single ceramic module, similar to Intel's Xeon 5300 series Clovertown processor modules.[36]
The 7300 series uses Intel's Caneland (Clarksboro) platform.
Intel claims the 7300 series Xeons offer more than twice the performance per watt as Intel's previous generation 7100 series. The 7300 series' Caneland chipset provides a point to point interface allowing the full front side bus bandwidth per processor.
The 7xxx series is aimed at the large server market, supporting configurations of up to 32 CPUs per host.
| Model | Speed | L2 cache | FSB | TDP |
|---|---|---|---|---|
| E7310 | 1.60 GHz | 2×2 MB | 1066 MT/s | 80 W |
| E7320 | 2.13 GHz | |||
| E7330 | 2.40 GHz | 2×3 MB | ||
| E7340 | 2×4 MB | |||
| L7345 | 1.86 GHz | 50 W | ||
| X7350 | 2.93 GHz | 130 W |
| General information | |
|---|---|
| Launched | 2008 |
| Discontinued | present |
| CPUID code | 106D1 |
| Product code | 80582 |
| Performance | |
| Max.CPUclock rate | 2.133 GHz to 2.66 GHz |
| FSB speeds | 1066 MT/s |
| Cache | |
| L1cache | 6 × 96 KB |
| L2 cache | 3 × 3 MB |
| L3 cache | 16 MB |
| Architecture and classification | |
| Application | MP Server |
| Technology node | 45 nm |
| Microarchitecture | Penryn |
| Instruction set | x86-16,IA-32,x86-64 |
| Physical specifications | |
| Cores |
|
| Package | |
| Products, models, variants | |
| Brand name |
|
Dunnington[37] – the last CPU of the Penryn generation and Intel's firstmulti-core (above two) die – features a single-die six- (orhexa-) core design with three unified 3 MB L2 caches (resembling three merged45 nm dual-core Wolfdale-3M dies), and 96 kB L1 cache (Data) and 16 MB of L3 cache. It features a 1.07 GT/sFSB, fits into the Tigerton's mPGA604 socket, and is compatible with both the Intel Caneland and IBM X4 chipsets. These processors support DDR2-1066 (533 MHz), and have a maximumTDP below 130 W. They are intended for blades and other stacked computer systems. Availability was scheduled for the second half of 2008. It was followed shortly by theNehalem microarchitecture. Total transistor count is 1.9 billion.[38]
Announced on September 15, 2008.[39]
| Model | Speed | L3 cache | FSB | TDP | Cores |
|---|---|---|---|---|---|
| E7420 | 2.13 GHz | 8 MB | 1066 MT/s | 90 W | 4 |
| E7430 | 12 MB | ||||
| E7440 | 2.40 GHz | 16 MB | |||
| L7445 | 2.13 GHz | 12 MB | 50 W | ||
| E7450 | 2.40 GHz | 90 W | 6 | ||
| L7455 | 2.13 GHz | 65 W | |||
| X7460 | 2.66 GHz | 16 MB | 130 W |
Xeon 3400-series processors based onLynnfield are designed for entry-level servers compared to Bloomfield, which is designed for uniprocessor workstations. Like Bloomfield, they are quad-core single-package processors based on theNehalem microarchitecture, but were introduced almost a year later, in September 2009. The same processors are marketed for mid-range to high-end desktops systems asCore i5 andCore i7. They have two integrated memory channels as well asPCI Express andDirect Media Interface (DMI) links, but noQuickPath Interconnect (QPI) interface.
At low end of the 3400-series is not a Lynnfield but aClarkdale processor, which is also used in the Core i3-500 and Core i5-600 processors as well as the Celeron G1000 and G6000 Pentium series. A single model was released in March 2010, the Xeon L3406. Compared to all other Clarkdale-based products, this one does not support integrated graphics, but has a much lower thermal design power of just 30 W. Compared to the Lynnfield-based Xeon 3400 models, it only offers two cores.
Bloomfield (orNehalem-E) is the codename for the successor to the Xeon 3300 series, is based on theNehalem microarchitecture and uses the same45 nm manufacturing methods as Intel'sPenryn. The first processor released with the Nehalem architecture is the high-end desktopCore i7, which was released in November 2008. This is the server version for single CPU systems.This is asingle-socket Intel Xeon processor designed for uniprocessor workstations.
The performance improvements over the previous Xeon 3300 series are based mainly on:
| Model | Speed | L3 cache | QPI speed | DDR3 speed | TDP | Cores | Threads | Turbo-Boost |
|---|---|---|---|---|---|---|---|---|
| W3503 | 2.40 GHz | 4 MB | 4.8 GT/s | 1066 MT/s | 130 W | 2 | No | |
| W3505 | 2.53 GHz | |||||||
| W3520 | 2.66 GHz | 8 MB | 4 | 8 | Yes | |||
| W3530 | 2.80 GHz | |||||||
| W3540 | 2.93 GHz | |||||||
| W3550 | 3.06 GHz | |||||||
| W3565 | 3.20 GHz | |||||||
| W3570 | 3.2 GHz | 6.4 GT/s | 1333 MT/s | |||||
| W3580 | 3.33 GHz | |||||||
| General information | |
|---|---|
| Launched | 2008 |
| Discontinued | present |
| CPUID code | 106Ax |
| Product code | 80602 |
| Performance | |
| Max.CPUclock rate | 1.866 GHz to 3.333 GHz |
| Cache | |
| L2 cache | 4×256 kB |
| L3 cache | 8 MB |
| Architecture and classification | |
| Application | DP Server |
| Technology node | 45 nm |
| Microarchitecture | Nehalem |
| Instruction set | x86-16,IA-32,x86-64 |
| Physical specifications | |
| Cores |
|
| Package | |
| Products, models, variants | |
| Brand name |
|
Gainestown orNehalem-EP (Efficient Performance), the successor to Wolfdale-DP, and Harpertown, is based on theNehalem microarchitecture and uses the same45 nm manufacturing methods. The first processor released with the Nehalem microarchitecture is the high-end desktopCore i7, which was released in November 2008. Server processors of the Xeon 55xx range were first supplied to testers in December 2008.[40]
The performance improvements over Wolfdale-DP and Harpertown processors are based mainly on:
| Model | Speed | L3 cache | QPI speed | DDR3 speed | TDP | Cores | Threads | Turbo-Boost |
|---|---|---|---|---|---|---|---|---|
| E5502 | 1.87 GHz | 4 MB | 4.8 GT/s | 800 MT/s | 80 W | 2 | No | |
| E5503 | 2.00 GHz | |||||||
| E5504 | 4 | 4 | ||||||
| E5506 | 2.13 GHz | |||||||
| L5506 | 60 W | |||||||
| E5507 | 2.26 GHz | 80 W | ||||||
| L5518 | 2.13 GHz | 8 MB | 5.86 GT/s | 1066 MT/s | 60 W | 8 | Yes | |
| E5520 | 2.26 GHz | 80 W | ||||||
| L5520 | 60 W | |||||||
| E5530 | 2.40 GHz | 80 W | ||||||
| L5530 | 60 W | |||||||
| E5540 | 2.53 GHz | 80 W | ||||||
| X5550 | 2.66 GHz | 6.4 GT/s | 1333 MT/s | 95 W | ||||
| X5560 | 2.80 GHz | |||||||
| X5570 | 2.93 GHz | |||||||
| W5580 | 3.20 GHz | 130 W | ||||||
| W5590 | 3.33 GHz | |||||||
| General information | |
|---|---|
| Launched | 2010 |
| Discontinued | present |
| CPUID code | 106Ex |
| Product code | 80612 |
| Performance | |
| Max.CPUclock rate | 1.733 GHz to 2.40 GHz |
| Cache | |
| L2 cache | 4×256 kB |
| L3 cache | 8 MB |
| Architecture and classification | |
| Application | UP/DP Server |
| Technology node | 45 nm |
| Microarchitecture | Nehalem |
| Instruction set | x86-16,IA-32,x86-64 |
| Physical specifications | |
| Cores |
|
| Package | |
| Products, models, variants | |
| Brand names |
|
Jasper Forest is a Nehalem-based embedded processor withPCI Express connections on-die, core counts from 1 to 4 cores and power envelopes from 23 to 85 watts.[41]
The uni-processor version without QPI comes as LC35xx and EC35xx, while the dual-processor version is sold as LC55xx and EC55xx and uses QPI for communication between the processors. Both versions use a DMI link to communicate with the 3420 that is also used in the 3400-series Lynfield Xeon processors, but use anLGA 1366 package that is otherwise used for processors with QPI but no DMI or PCI Express links. The CPUID code of both Lynnfield and Jasper forest is 106Ex, i.e., family 6, model 30.
TheCeleron P1053 belongs into the same family as the LC35xx series, but lacks someRAS features that are present in the Xeon version.
Gulftown andWestmere-EP, six-core 32 nm architectureWestmere-based processors, are the basis for the Xeon 36xx and 56xx series and theCore i7-980X. It launched in the first quarter of 2010. The 36xx-series follows the 35xx-series Bloomfield uni-processor model while the 56xx-series follows the 55xx-series Gainestown dual-processor model and both are socket compatible to their predecessors.
| Model | Speed | L3 cache | QPI speed | DDR3 speed | TDP | Cores | Threads | Turbo-Boost |
|---|---|---|---|---|---|---|---|---|
| W3670 | 3.20 GHz | 12 MB | 4.8 GT/s | 1066 MT/s | 130 W | 6 | 12 | Yes |
| W3680 | 3.33 GHz | 6.4 GT/s | 1333 MT/s | |||||
| W3690 | 3.46 GHz | |||||||
| E5603 | 1.60 GHz | 4 MB | 4.8 GT/s | 800 MT/s | 80 W | 4 | 4 | No |
| E5606 | 2.13 GHz | 8 MB | 1066 MT/s | |||||
| E5607 | 2.26 GHz | |||||||
| L5609 | 1.86 GHz | 12 MB | 40 W | |||||
| L5618 | 5.86 GT/s | 8 | Yes | |||||
| E5620 | 2.40 GHz | 80 W | ||||||
| L5630 | 2.13 GHz | 40 W | ||||||
| E5630 | 2.53 GHz | 80 W | ||||||
| L5638 | 2.00 GHz | 1333 MT/s | 60 W | 6 | 12 | |||
| L5639 | 2.13 GHz | |||||||
| L5640 | 2.26 GHz | |||||||
| E5640 | 2.66 GHz | 1066 MT/s | 80 W | 4 | 8 | |||
| L5645 | 2.40 GHz | 1333 MT/s | 60 W | 6 | 12 | |||
| E5645 | 80 W | |||||||
| E5649 | 2.53 GHz | |||||||
| X5650 | 2.66 GHz | 6.4 GT/s | 95 W | |||||
| X5660 | 2.80 GHz | |||||||
| X5667 | 3.06 GHz | 4 | 8 | |||||
| X5670 | 2.93 GHz | 6 | 12 | |||||
| X5672 | 3.20 GHz | 4 | 8 | |||||
| X5675 | 3.06 GHz | 6 | 12 | |||||
| X5677 | 3.46 GHz | 130 W | 4 | 8 | ||||
| X5679 | 3.20 GHz | 1066 MT/s | 115 W | 6 | 12 | |||
| X5680 | 3.33 GHz | 1333 MT/s | 130 W | |||||
| X5687 | 3.60 GHz | 4 | 8 | |||||
| X5690 | 3.46 GHz | 6 | 12 | |||||
| X5698 | 4.40 GHz | 1066 MT/s | 2 | 4 | No |
 Xeon E7530 (with and without the heat spreader) | |
| General information | |
|---|---|
| Launched | March 30, 2010; 15 years ago (2010-03-30) |
| Discontinued | Q4 2012 |
| Marketed by | Intel |
| Designed by | Intel |
| Common manufacturer | |
| CPUID code | 206Ex |
| Product code | 80604 |
| Performance | |
| Max.CPUclock rate | 1.733 GHz to 2.667 GHz |
| QPI speeds | 6.4 GT/s |
| Cache | |
| L2 cache | 256 KB per core |
| L3 cache | Up to 24 MB |
| Architecture and classification | |
| Application | DP/MP Server |
| Technology node | 45 nm |
| Microarchitecture | Nehalem |
| Instruction set | x86-16,IA-32,x86-64 |
| Physical specifications | |
| Cores |
|
| Package | |
| Products, models, variants | |
| Brand names |
|
Beckton orNehalem-EX (Expandable server market) is a Nehalem-based processor with up to eight cores and uses buffering inside the chipset to support up to 16 standard DDR3 DIMMs per CPU socket without requiring the use of FB-DIMMs.[42] Unlike all previous Xeon MP processors, Nehalem-EX uses the newLGA 1567 (Socket LS) package, replacing theSocket 604 used in the previous models, up to Xeon7400 "Dunnington". The 75xx models have four QuickPath interfaces, so it can be used in up-to eight-socket configurations, while the 65xx models are only for up to two sockets. Designed by the Digital Enterprise Group (DEG) Santa Clara and Hudson Design Teams, Beckton is manufactured on the P1266 (45 nm) technology. Its launch in March 2010 coincided with that of its direct competitor, AMD'sOpteron 6xxx "Magny-Cours".[43]
Most models limit the number of cores and QPI links as well as the L3 cache size in order to get a broader range of products out of the single chip design.
Westmere-EX is the follow-on to Beckton/Nehalem-EX and the first Intel processor to have ten CPU cores. The microarchitecture is the same as in the six-core Gulftown/Westmere-EP processor, but it uses theLGA 1567 package like Beckton to support up to eight sockets.
Starting with Westmere-EX, the naming scheme has changed once again, with "E7-xxxx" now signifying the high-end line of Xeon processors using a package that supports larger than two-CPU configurations, formerly the 7xxx series. Similarly, the 3xxx uniprocessor and 5xxx dual-processor series turned into E3-xxxx and E5-xxxx, respectively, for later processors.
TheXeon E3-12xx line of processors, introduced in April 2011, uses theSandy Bridge chips that are also the base for the Core i3/i5/i7-2xxx and Celeron/Pentium Gxxx products using the sameLGA 1155 socket, but with a different set of features disabled. Notably, the Xeon variants include support forECC memory,VT-d andtrusted execution that are not present on the consumer models, while only some Xeon E3 enable the integratedGPU that is present on Sandy Bridge. Like its Xeon 3400-series predecessors, the Xeon E3 only supports operation with a single CPU socket and is targeted at entry-level workstations and servers. The CPUID of this processor is 0206A7h, the product code is 80623.
Xeon E3-12xx v2 is a minor update of the Sandy Bridge-based E3-12xx, using the 22 nm shrink, and providing slightly better performance while remaining backwards compatible. They were released in May 2012 and mirror the desktop Core i3/i5/i7-3xxx parts.
TheXeon E5-16xx processors follow the previous Xeon 3500/3600-series products as the high-end single-socket platform, using theLGA 2011 package introduced with this processor. They share the Sandy Bridge-E platform with the single-socket Core i7-38xx and i7-39xx processors. The CPU chips have no integrated GPU but eight CPU cores, some of which are disabled in the entry-level products. TheXeon E5-26xx line has the same features but also enables multi-socket operation like the earlier Xeon 5000-series and Xeon 7000-series processors.
TheXeon E5 v2 line was an update, released in September 2013 to replace the original Xeon E5 processors with a variant based on the Ivy Bridge shrink. The maximum number of CPU cores was raised to 12 per processor module and the total L3 cache was upped to 30 MB.[44][45] The consumer version of the Xeon E5-16xx v2 processor is theCore i7-48xx and 49xx.
TheXeon E7 v2 line was an update, released in February 2014 to replace the original Xeon E7 processors with a variant based on the Ivy Bridge shrink. There was no Sandy Bridge version of these processors but rather a Westmere version.
Introduced in May 2013,Xeon E3-12xx v3 is the first Xeon series based on the Haswell microarchitecture. It uses the newLGA 1150 socket, which was introduced with the desktop Core i5/i7 Haswell processors, incompatible with the LGA 1155 that was used in Xeon E3 and E3 v2. As before, the main difference between the desktop and server versions is added support for ECC memory in the Xeon-branded parts. The main benefit of the new microarchitecture is better power efficiency.
Introduced in September 2014,Xeon E5-16xx v3 andXeon E5-26xx v3 series use the newLGA 2011-v3 socket, which is incompatible with the LGA 2011 socket used by earlier Xeon E5 and E5 v2 generations based on Sandy Bridge and Ivy Bridge microarchitectures. Some of the main benefits of this generation, compared to the previous one, are improved power efficiency, higher core counts, and biggerlast level caches (LLCs). Following the already used nomenclature, Xeon E5-26xx v3 series allows dual-socket operation.
One of the new features of this generation is that Xeon E5 v3 models with more than 10 cores supportcluster on die (COD) operation mode, allowing CPU's multiple columns of cores and LLC slices to be logically divided into what is presented as twonon-uniform memory access (NUMA) CPUs to the operating system. By keeping data and instructions local to the "partition" of CPU which is processing them, thus decreasing the LLC access latency, COD brings performance improvements to NUMA-aware operating systems and applications.[46]
Introduced in May 2015,Xeon E7-48xx v3 andXeon E7-88xx v3 series provide higher core counts, higher per-core performance and improved reliability features, compared to the previous Xeon E7 v2 generation. Following the usual SKU nomenclature, Xeon E7-48xx v3 and E7-88xx v3 series allow multi-socket operation, supporting up to quad- and eight-socket configurations, respectively.[47][48] These processors use the LGA 2011 (R1) socket.[49]
Xeon E7-48xx v3 and E7-88xx v3 series contain a quad-channelintegrated memory controller (IMC), supporting both DDR3 and DDR4LRDIMM orRDIMM memory modules through the use ofJordan Creek (DDR3) orJordan Creek 2 (DDR4) memory buffer chips. Both versions of the memory buffer chip connect to the processor using version 2.0 of the IntelScalable Memory Interconnect (SMI) interface, while supportinglockstep memory layouts for improved reliability. Up to four memory buffer chips can be connected to a processor, with up to six DIMM slots supported per each memory buffer chip.[47][48]
Xeon E7-48xx v3 and E7-88xx v3 series also contain functional bug-free support forTransactional Synchronization Extensions (TSX), which was disabled via amicrocode update in August 2014 for Haswell-E, Haswell-WS (E3-12xx v3) and Haswell-EP (E5-16xx/26xx v3) models, due to a bug that was discovered in the TSX implementation.[47][48][50][51][52][53]
Introduced in June 2015,Xeon E3-12xx v4 is the first Xeon series based on the Broadwell microarchitecture. It usesLGA 1150 socket, which was introduced with the desktop Core i5/i7 Haswell processors. As before, the main difference between the desktop and server versions is added support for ECC memory in the Xeon-branded parts. The main benefit of the new microarchitecture is the new lithography process, which results in better power efficiency.
Introduced in October 2015,Xeon E3-12xx v5 is the first Xeon series based on the Skylake microarchitecture. It uses newLGA 1151 socket, which was introduced with the desktop Core i5/i7 Skylake processors. Although it uses the same socket as consumer processors, it is limited to the C200 server chipset series and will not work with consumer chipsets like Z170. As before, the main difference between the desktop and server versions is added support for ECC memory in the Xeon-branded parts.
Introduced in January 2017,Xeon E3-12xx v6 is the first Xeon series based on the Kaby Lake microarchitecture. It uses the sameLGA 1151 socket, which was introduced with the desktop Core i5/i7 Kaby Lake processors. As before, the main difference between the desktop and server versions is added support for ECC memory and improved energy efficiency in the Xeon-branded parts.
| Processor branding | Model | Cores (Threads) | Base CPU clock rate | Max.Turbo clock rate | GPU | maxGPU clock rate | L3 cache[note 1] | TDP | Memory support | Price (USD) |
|---|---|---|---|---|---|---|---|---|---|---|
| Xeon E | 2186G | 6 (12) | 3.8 GHz | 4.7 GHz | UHD P630 | 1.20 GHz | 12 MB | 95 W | Up to 64 GB[note 2] DDR4 2666 ECC memory supported | $506 |
| 2176G | 3.7 GHz | 80 W | $406 | |||||||
| 2174G | 4 (8) | 3.8 GHz | 8 MB | 71 W | $370 | |||||
| 2146G | 6 (12) | 3.5 GHz | 4.5 GHz | 12 MB | 80 W | $350 | ||||
| 2144G | 4 (8) | 3.6 GHz | 8 MB | 71 W | $306 | |||||
| 2136 | 6 (12) | 3.3 GHz | N/A | 12 MB | 80 W | $319 | ||||
| 2134 | 4 (8) | 3.5 GHz | 8 MB | 71 W | $281 | |||||
| 2126G | 6 (6) | 3.3 GHz | UHD P630 | 1.20 GHz | 12 MB | 80 W | $286 | |||
| 2124G | 4 (4) | 3.4 GHz | 8 MB | 71 W | $245 | |||||
| 2124 | 3.3 GHz | 4.3 GHz | N/A | $217 | ||||||
| 2104G | 3.2 GHz | N/A | UHD P630 | 1.20 GHz | 65 W | $193 | ||||
| Processor branding | Model | Cores (Threads) | Base CPU clock rate | Max.Turbo clock rate | GPU | maxGPU clock rate | L3 cache[note 3] | TDP | Memory support | Price (USD) |
|---|---|---|---|---|---|---|---|---|---|---|
| Xeon E | 2288G | 8 (16) | 3.7 GHz | 5.0 GHz | UHD P630 | 1.20 GHz | 16 MiB | 95 W | Up to 128 GB[note 4] DDR4 2666 ECC memory supported | $539 |
| 2286G | 6 (12) | 4.0 GHz | 4.9 GHz | 12 MiB | $450 | |||||
| 2278G | 8 (16) | 3.4 GHz | 5.0 GHz | 16 MiB | 80 W | $494 | ||||
| 2276G | 6 (12) | 3.8 GHz | 4.9 GHz | 12 MiB | $362 | |||||
| 2274G | 4 (8) | 4.0 GHz | 8 MiB | 83 W | $328 | |||||
| 2246G | 6 (12) | 3.6 GHz | 4.8 GHz | 12 MiB | 80 W | $311 | ||||
| 2244G | 4 (8) | 3.8 GHz | 8 MiB | 71 W | $272 | |||||
| 2236 | 6 (12) | 3.4 GHz | N/A | 12 MiB | 80 W | $284 | ||||
| 2234 | 4 (8) | 3.6 GHz | 8 MiB | 71 W | $250 | |||||
| 2226G | 6 (6) | 3.4 GHz | 4.7 GHz | UHD P630 | 1.20 GHz | 12 MiB | 80 W | $255 | ||
| 2224G | 4 (4) | 3.5 GHz | 8 MiB | 71 W | $213 | |||||
| 2224 | 3.4 GHz | 4.6 GHz | N/A | $193 | ||||||
The 3rd generation Xeon SP processors for 4S and 8S.
The 3rd generation Xeon SP processors for WS, 1S and 2S.
Introduced in 2023, the4th generation Xeon Scalable processors (Sapphire Rapids-SP andSapphire Rapids-HBM) andXeon W-2400 andW-3400 series (Sapphire Rapids-WS) provide large performance enhancements over the prior generation.
TSXLDTRK)Not all accelerators are available in all processor models. Some accelerators are available under the Intel On Demand program, also known as Software Defined Silicon (SDSi), where a license is required to activate a given accelerator that is physically present in the processor. The license can be obtained as a one-time purchase or as a paid subscription. Activating the license requires support in the operating system. A driver with the necessary support was added in Linux kernel version 6.2.
Diamond Rapids is slated for 2026.[54] Diamond Rapids will use a new socket type, and support PCIe 6.0 as well as CXL 3.[55]
By 2013 Xeon processors were ubiquitous in supercomputers—more than 80% of theTOP500 machines in 2013 used them. For the fastest machines, much of the performance comes from compute accelerators; Intel's entry into that market was theXeon Phi, the first machines using it appeared in June 2012 and by June 2013 it was used in the fastest computer in the world.
June 29, 1998 Intel® Pentium® II Xeon™ Processor 400 MHz
Under a complex set of internal timing conditions and system events, software using the Intel TSX (Transactional Synchronization Extensions) instructions may observe unpredictable system behavior.
