x86-64 (also known asx64,x86_64,AMD64, andIntel 64)[note 1] is a64-bit extension of thex86instruction set architecture first announced in 1999. It introduces two new operating modes: 64-bit mode and compatibility mode, along with a new four-levelpaging mechanism.
In 64-bit mode, x86-64 supports significantly large amounts ofvirtual memory andphysical memory compared to its32-bit predecessors, allowing programs to utilize more memory for data storage. The architecture expands the number ofgeneral-purpose registers from 8 to 16, all fully general-purpose, and extends their width to 64 bits.
Floating-point arithmetic is supported through mandatorySSE2 instructions in 64-bit mode. While the olderx87 FPU and MMX registers are still available, they are generally superseded by a set of sixteen 128-bitvector registers (XMM registers). Each of these vector registers can store one or twodouble-precision floating-point numbers, up to foursingle-precision floating-point numbers, or various integer formats.
In 64-bit mode, instructions are modified to support 64-bitoperands and 64-bitaddressing mode.
The x86-64 architecture defines a compatibility mode that allows 16-bit and 32-bituser applications to run unmodified alongside 64-bit applications, provided the 64-bit operating system supports them.[11][note 2] Since the full x86-32 instruction sets remain implemented in hardware without the need for emulation, these olderexecutables can run with little or no performance penalty,[13] while newer or modified applications can take advantage of new features of the processor design to achieve performance improvements. Also, processors supporting x86-64 still power on inreal mode to maintainbackward compatibility with the original8086 processor, as has been the case with x86 processors since the introduction ofprotected mode with the80286.
The original specification, created byAMD and released in 2000, has been implemented by AMD,Intel, andVIA. TheAMD K8microarchitecture, in theOpteron andAthlon 64 processors, was the first to implement it. This was the first significant addition to thex86 architecture designed by a company other than Intel. Intel was forced to follow suit and introduced a modifiedNetBurst family which was software-compatible with AMD's specification.VIA Technologies introduced x86-64 in their VIA Isaiah architecture, with theVIA Nano.
The x86-64 architecture was quickly adopted for desktop and laptop personal computers and servers which were commonly configured for 16 GiB (gibibytes) of memory or more. It has effectively replaced the discontinued IntelItanium architecture (formerlyIA-64), which was originally intended to replace the x86 architecture. x86-64 and Itanium are not compatible on the native instruction set level, and operating systems and applications compiled for one architecture cannot be run on the other natively.
AMD64 (also variously referred to byAMD in their literature and documentation as “AMD 64-bit Technology” and “AMD x86-64 Architecture”) was created as an alternative to the radically differentIA-64 architecture designed byIntel andHewlett-Packard, which wasbackward-incompatible withIA-32, the 32-bit version of thex86 architecture. AMD originally announced AMD64 in 1999[14] with a full specification available in August 2000.[15] As AMD was never invited to be a contributing party for the IA-64 architecture and any kind of licensing seemed unlikely, the AMD64 architecture was positioned by AMD from the beginning as an evolutionary way to add64-bit computing capabilities to the existing x86 architecture while supporting legacy 32-bit x86code, as opposed to Intel's approach of creating an entirely new, completely x86-incompatible 64-bit architecture with IA-64.
The first AMD64-based processor, theOpteron, was released in April 2003.
AMD's processors implementing the AMD64 architecture includeOpteron,Athlon 64,Athlon 64 X2,Athlon 64 FX,Athlon II (followed by "X2", "X3", or "X4" to indicate the number of cores, and XLT models),Turion 64,Turion 64 X2,Sempron ("Palermo" E6 stepping and all "Manila" models),Phenom (followed by "X3" or "X4" to indicate the number of cores),Phenom II (followed by "X2", "X3", "X4" or "X6" to indicate the number of cores),FX,Fusion/APU andRyzen/Epyc.
The primary defining characteristic of AMD64 is the availability of 64-bit general-purposeprocessor registers (for example,rax), 64-bitinteger arithmetic and logical operations, and 64-bitvirtual addresses.[16] The designers took the opportunity to make other improvements as well.
Notable changes in the 64-bit extensions include:
Although virtual addresses are 64 bits wide in 64-bit mode, current implementations (and all chips that are known to be in the planning stages) do not allow the entire virtual address space of 264 bytes (16 EiB) to be used. This would be approximately four billion times the size of the virtual address space on 32-bit machines. Most operating systems and applications will not need such a large address space for the foreseeable future, so implementing such wide virtual addresses would simply increase the complexity and cost of address translation with no real benefit. AMD, therefore, decided that, in the first implementations of the architecture, only the least significant 48 bits of a virtual address would actually be used in address translation (page table lookup).[11]: 120
In addition, the AMD specification requires that the most significant 16 bits of any virtual address, bits 48 through 63, must be copies of bit 47 (in a manner akin tosign extension). If this requirement is not met, the processor will raise an exception.[11]: 131 Addresses complying with this rule are referred to as "canonical form."[11]: 130 Canonical form addresses run from 0 through 00007FFF'FFFFFFFF, and from FFFF8000'00000000 through FFFFFFFF'FFFFFFFF, for a total of 256 TiB of usable virtual address space. This is still 65,536 times larger than the virtual 4 GiB address space of 32-bit machines.
This feature eases later scalability to true 64-bit addressing. Many operating systems (including, but not limited to, theWindows NT family) take the higher-addressed half of the address space (namedkernel space) for themselves and leave the lower-addressed half (user space) for application code, user mode stacks, heaps, and other data regions.[23] The "canonical address" design ensures that every AMD64 compliant implementation has, in effect, two memory halves: the lower half starts at 00000000'00000000 and "grows upwards" as more virtual address bits become available, while the higher half is "docked" to the top of the address space and grows downwards. Also, enforcing the "canonical form" of addresses by checking the unused address bits prevents their use by the operating system intagged pointers as flags, privilege markers, etc., as such use could become problematic when the architecture is extended to implement more virtual address bits.
The first versions of Windows for x64 did not even use the full 256 TiB; they were restricted to just 8 TiB of user space and 8 TiB of kernel space.[23] Windows did not support the entire 48-bit address space untilWindows 8.1, which was released in October 2013.[23]
The 64-bit addressing mode ("long mode") is a superset ofPhysical Address Extensions (PAE); because of this,page sizes may be 4 KiB (212 bytes) or 2 MiB (221 bytes).[11]: 120 Long mode also supports page sizes of 1 GiB (230 bytes).[11]: 120 Rather than the three-levelpage table system used by systems in PAE mode, systems running inlong mode use four levels of page table: PAE'sPage-Directory Pointer Table is extended from four entries to 512, and an additionalPage-Map Level 4 (PML4) Table is added, containing 512 entries in 48-bit implementations.[11]: 131 A full mapping hierarchy of 4 KiB pages for the whole 48-bit space would take a bit more than 512 GiB of memory (about 0.195% of the 256 TiB virtual space).
| Bits: | 63 | 62 ... 52 | 51 ... 32 | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Content: | NX | reserved | Bit 51...32 of base address | |||||||||||||||||||||||||||||
| Bits: | 31 ... 12 | 11 ... 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||||||||||||||||
| Content: | Bit 31...12 of base address | ign. | G | PAT | D | A | PCD | PWT | U/S | R/W | P | |||||||||||||||||||||
Intel has implemented a scheme with a5-level page table, which allows Intel 64 processors to support 57-bit addresses, and in turn, a 128 PiB virtual address space.[24] Further extensions may allow full 64-bit virtual address space and physical memory with 12-bit page table descriptors and 16- or 21-bit memory offsets for 64 KiB and 2 MiB page allocation sizes; the page table entry would be expanded to 128 bits to support additional hardware flags for page size and virtual address space size.[25]
The operating system can also limit the virtual address space. Details, where applicable, are given in the "Operating system compatibility and characteristics" section.
Current AMD64 processors support a physical address space of up to 248 bytes of RAM, or 256 TiB.[19] However, as of 2020[update], there were no known x86-64motherboards that support 256 TiB of RAM.[26][27][28][29][failed verification] The operating system may place additional limits on the amount of RAM that is usable or supported. Details on this point are given in the "Operating system compatibility and characteristics" section of this article.
The architecture has two primary modes of operation: long mode and legacy mode.
| Operating | Operating system required | Type of code being run | Size (in bits) | No. ofgeneral-purpose registers | ||
|---|---|---|---|---|---|---|
| Mode | Sub-mode | Addresses | Operands (default in italics) | |||
| Long mode | 64-bit mode | 64-bit OS, 64-bitUEFI firmware, or the previous two interacting via a 64-bit firmware's UEFI interface | 64-bit | 64 | 8, 16,32, 64 | 16 |
| Compatibility mode | Bootloader or 64-bit OS | 32-bit | 32 | 8, 16,32 | 8 | |
| 16-bit protected mode | 16 | 8,16, 32 | 8 | |||
| Legacy mode | Protected mode | Bootloader, 32-bit OS, 32-bit UEFI firmware, or the latter two interacting via the firmware's UEFI interface | 32-bit | 32 | 8, 16,32 | 8 |
| 16-bit protected mode OS | 16-bit protected mode | 16 | 8,16, 32[m 1] | 8 | ||
| Virtual 8086 mode | 16-bit protected mode or 32-bit OS | subset ofreal mode | 16 | 8,16, 32[m 1] | 8 | |
| Unreal mode | Bootloader or real mode OS | real mode | 16, 20, 32 | 8,16, 32[m 1] | 8 | |
| Real mode | Bootloader, real mode OS, or any OS interfacing with a firmware'sBIOS interface[30] | real mode | 16, 20,21 | 8,16, 32[m 1] | 8 | |
Long mode is the architecture's intended primary mode of operation; it is a combination of the processor's native 64-bit mode and a combined 32-bit and 16-bit compatibility mode. It is used by 64-bit operating systems. Under a 64-bit operating system, 64-bit programs run under 64-bit mode, and 32-bit and 16-bit protected mode applications (that do not need to use either real mode or virtual 8086 mode in order to execute at any time) run under compatibility mode. Real-mode programs and programs that use virtual 8086 mode at any time cannot be run in long mode unless those modes are emulated in software.[11]: 11 However, such programs may be started from an operating system running in long mode on processors supportingVT-x orAMD-V by creating a virtual processor running in the desired mode.
Since the basicinstruction set is the same, there is almost no performance penalty for executing protected mode x86 code. This is unlike Intel'sIA-64, where differences in the underlying instruction set mean that running 32-bit code must be done either in emulation of x86 (making the process slower) or with a dedicated x86 coprocessor. However, on the x86-64 platform, many x86 applications could benefit from a 64-bitrecompile, due to the additional registers in 64-bit code and guaranteed SSE2-based FPU support, which acompiler can use for optimization. However, applications that regularly handle integers wider than 32 bits, such as cryptographic algorithms, will need a rewrite of the code handling the huge integers in order to take advantage of the 64-bit registers.
Legacy mode is the mode that the processor is in when it is not in long mode.[11]: 14 In this mode, the processor acts like an older x86 processor, and only 16-bit and 32-bit code can be executed. Legacy mode allows for a maximum of 32 bit virtual addressing which limits the virtual address space to 4 GiB.[11]: 14 : 24 : 118 64-bit programs cannot be run from legacy mode.
Protected mode is made into a submode of legacy mode.[11]: 14 It is the submode that 32-bit operating systems and 16-bit protected mode operating systems operate in when running on an x86-64 CPU.[11]: 14
Real mode is the initial mode of operation when the processor is initialized, and is a submode of legacy mode. It is backwards compatible with the originalIntel 8086 andIntel 8088 processors. Real mode is primarily used today by operating system bootloaders, which are required by the architecture to configurevirtual memory details before transitioning to higher modes. This mode is also used by any operating system that needs to communicate with the system firmware with a traditionalBIOS-style interface.[30]
Intel 64 is Intel's implementation of x86-64, used and implemented in various processors made by Intel.
Historically, AMD has developed and produced processors with instruction sets patterned after Intel's original designs, but with x86-64, roles were reversed: Intel found itself in the position of adopting theISA that AMD created as an extension to Intel's own x86 processor line.
Intel's project was originallycodenamedYamhill[31] (after theYamhill River in Oregon's Willamette Valley). After several years of denying its existence, Intel announced at the February 2004IDF that the project was indeed underway. Intel's chairman at the time,Craig Barrett, admitted that this was one of their worst-kept secrets.[32][33]
Intel's name for this instruction set has changed several times. The name used at the IDF wasCT[34] (presumably[original research?] forClackamas Technology, another codename from anOregon river); within weeks they began referring to it asIA-32e (forIA-32 extensions) and in March 2004 unveiled the "official" nameEM64T (Extended Memory 64 Technology). In late 2006 Intel began instead using the nameIntel 64 for its implementation, paralleling AMD's use of the name AMD64.[35]
The first processor to implement Intel 64 was the multi-socket processorXeon code-namedNocona in June 2004. In contrast, the initial Prescott chips (February 2004) did not enable this feature. Intel subsequently began selling Intel 64-enabled Pentium 4s using the E0 revision of the Prescott core, being sold on the OEM market as the Pentium 4, model F. The E0 revision also adds eXecute Disable (XD) (Intel's name for theNX bit) to Intel 64, and has been included in then current Xeon code-namedIrwindale. Intel's official launch of Intel 64 (under the name EM64T at that time) in mainstream desktop processors was the N0 stepping Prescott-2M.
The first Intelmobile processor implementing Intel 64 is theMerom version of theCore 2 processor, which was released on July 27, 2006. None of Intel's earlier notebook CPUs (Core Duo,Pentium M,Celeron M,Mobile Pentium 4) implement Intel 64.
Intel's processors implementing the Intel64 architecture include thePentium 4 F-series/5x1 series, 506, and 516,Celeron D models 3x1, 3x6, 355, 347, 352, 360, and 365 and all laterCelerons, all models ofXeon since "Nocona", all models ofPentium Dual-Core processors since "Merom-2M", theAtom 230, 330, D410, D425, D510, D525, N450, N455, N470, N475, N550, N570, N2600 and N2800, all versions of thePentium D,Pentium Extreme Edition,Core 2,Core i9,Core i7,Core i5, andCore i3 processors, and theXeon Phi 7200 series processors.
X86S was a simplification of x86-64 first proposed by Intel in May 2023.[36] The new architecture would have removed support for 16-bit and 32-bit operating systems, although 32-bit programs would still run under a 64-bit OS. A compliant CPU would have no longer hadlegacy mode, and started directly in 64-bitlong mode. There would have been a way to switch to5-level paging without going through the unpaged mode. Specific removed features included:[37]
The draft specification received multiple updates, reaching version 1.2 by June 2024. It was eventually abandoned as of December 2024, following the formation of thex86 Ecosystem Advisory Group by Intel and AMD.[38]
Advanced Performance Extensions is a 2023 Intel proposal for new instructions and an additional 16 general-purpose registers.
VIA Technologies introduced their first implementation of the x86-64 architecture in 2008 after five years of development by its CPU division,Centaur Technology.[39]Codenamed "Isaiah", the 64-bit architecture was unveiled on January 24, 2008,[40] and launched on May 29 under theVIA Nano brand name.[41]
The processor supports a number of VIA-specific x86 extensions designed to boost efficiency in low-power appliances.It is expected that the Isaiah architecture will be twice as fast in integer performance and four times as fast infloating-point performance as the previous-generationVIA Esther at an equivalentclock speed. Power consumption is also expected to be on par with the previous-generation VIA CPUs, withthermal design power ranging from 5 W to 25 W.[42]Being a completely new design, the Isaiah architecture was built with support for features like the x86-64 instruction set andx86 virtualization which were unavailable on its predecessors, theVIA C7 line, while retaining their encryption extensions.
In 2020, through a collaboration between AMD, Intel,Red Hat, andSUSE, three microarchitecture levels (or feature levels) on top of the x86-64 baseline were defined: x86-64-v2, x86-64-v3, and x86-64-v4.[43][44] These levels define specific features that can be targeted by programmers to provide compile-time optimizations. The features exposed by each level are as follows:[45]
| Level name | CPU features | Example instruction | Supported processors |
|---|---|---|---|
| (baseline) also as: x86-64-v1 | CMOV | cmov | baseline for all x86-64 CPUs
|
| CX8 | cmpxchg8b | ||
| FPU | fld | ||
| FXSR | fxsave | ||
| MMX | emms | ||
| OSFXSR | fxsave | ||
| SCE | syscall | ||
| SSE | cvtss2si | ||
| SSE2 | cvtpi2pd | ||
| x86-64-v2 | CMPXCHG16B | cmpxchg16b | IntelNehalem and newer Intel "big" cores |
| LAHF-SAHF | lahf | ||
| POPCNT | popcnt | ||
| SSE3 | addsubpd | ||
| SSE4_1 | blendpd | ||
| SSE4_2 | pcmpestri | ||
| SSSE3 | pshufb | ||
| x86-64-v3 | AVX | vzeroall | IntelHaswell and newer Intel "big" cores (AVX2 enabled models only) |
| AVX2 | vpermd | ||
| BMI1 | andn | ||
| BMI2 | bzhi | ||
| F16C | vcvtph2ps | ||
| FMA | vfmadd132pd | ||
| LZCNT | lzcnt | ||
| MOVBE | movbe | ||
| OSXSAVE | xgetbv | ||
| x86-64-v4 | AVX512F | kmovw | IntelSkylake and newer Intel "big" cores (AVX512 enabled models only) |
| AVX512BW | vdbpsadbw | ||
| AVX512CD | vplzcntd | ||
| AVX512DQ | vpmullq | ||
| AVX512VL | — |
The x86-64 microarchitecture feature levels can also be found as AMD64-v1, AMD64-v2 .. or AMD64_v1 .. in settings where the "AMD64" nomenclature is used. These are used as synonyms with the x86-64-vX nomenclature and are thus functionally identical. E.g. the Go language documentation or the Fedora linux distribution.
All levels include features found in the previous levels. Instruction set extensions not concerned with general-purpose computation, includingAES-NI andRDRAND, are excluded from the level requirements.
On any x86_64 Linux distribution, all x86_64 feature levels supported by a CPU can be verified using command:ld.so --help The result will be visible at the end of command's output:
Subdirectories of glibc-hwcaps directories, in priority order:x86-64-v4x86-64-v3 (supported, searched)x86-64-v2 (supported, searched)
Here x86-64-v4 feature level is not supported by CPU, but x86-64-v3 and x86-64-v2 are, which means this CPU does not support AVX512 required at v4 level.
Although nearly identical, there are some differences between the two instruction sets in the semantics of a few seldom used machine instructions (or situations), which are mainly used forsystem programming.[48] Unless instructed to otherwise via-march settings, compilers generally produceexecutables (i.e.machine code) that avoid any differences, at least for ordinaryapplication programs. This is therefore of interest mainly to developers of compilers, operating systems and similar, which must deal with individual and special system instructions.
SYSCALL/SYSRET only in 64-bit mode (not in compatibility mode),[49] and allowsSYSENTER/SYSEXIT in both modes.[50] AMD64 lacksSYSENTER/SYSEXIT in both sub-modes oflong mode.[11]: 33 SYSRET, AMD64 processors execute the general protection fault handler in privilege level 3,[51] while on Intel 64 processors it is executed in privilege level 0.[52]SYSRET instruction will load a set of fixed values into the hidden part of theSSsegment register (base-address, limit, attributes) on Intel 64 but leave the hidden part ofSS unchanged on AMD64.[53]SYSCFG,TOP_MEM, andTOP_MEM2.FXSAVE andFXRSTOR instructions).[clarification needed]REX.W prefix can be used with the far-pointer instructions (LFS,LGS,LSS,JMP FAR,CALL FAR) to increase the size of theirfar pointer argument to 80 bits (64-bit offset + 16-bit segment).MOVSXD instruction is executed with a memory source operand and an operand-size of 16 bits, the memory operand will be accessed with a 16-bit read on Intel 64, but a 32-bit read on AMD64.FCOMI/FCOMIP/FUCOMI/FUCOMIP (x87 floating-point compare) instructions will clear the OF, SF and AF bits ofEFLAGS on Intel 64, but leave these flag bits unmodified on AMD64.VMASKMOVPS/VMASKMOVPD/VPMASKMOVD/VPMASKMOVQ (AVX/AVX2 masked move to/from memory) instructions, Intel 64 architecturally guarantees that the instructions will not cause memory faults (e.g. page-faults and segmentation-faults) for any zero-masked lanes, while AMD64 does not provide such a guarantee.RDRAND instruction fails to obtain a random number (as indicated byEFLAGS.CF=0), the destination register is architecturally guaranteed to be set to 0 on Intel 64 but not AMD64.VPINSRD andVPEXTRD (AVX vector lane insert/extract) instructions outside 64-bit mode, AMD64 requires the instructions to be encoded withVEX.W=0, while Intel 64 also accepts encodings with VEX.W=1. (In 64-bit mode, both AMD64 and Intel 64 require VEX.W=0.)0F 0D /r opcode with theModR/M byte's Mod field set to11b is a Reserved-NOP on Intel 64[54] but will cause #UD (invalid-opcode exception) on AMD64.[55]LFENCE andMFENCE differ between Intel 64 and AMD64:LFENCE is dispatch-serializing (enabling it to be used as aspeculation fence) on Intel 64 but is not architecturally guaranteed to be dispatch-serializing on AMD64.[56]MFENCE is a fully serializing instruction (including instruction fetch serialization) on AMD64 but not Intel 64.MOV to CR8 andINVPCID instructions are serializing on AMD64 but not Intel 64.LMSW instruction is serializing on Intel 64 but not AMD64.WRMSR to thex2APIC ICR (Interrupt Command Register; MSR830h) is commonly used to produce an IPI (Inter-processor interrupt) — on Intel 64[57] but not AMD64[58] CPUs, such an IPI can be reordered before an older memory store. | This section needs to beupdated. The reason given is: future tense relating to processors that have been out for years, dates with day and month but no year. Please help update this article to reflect recent events or newly available information.(January 2023) |
CMPXCHG16B instruction, which is an extension of theCMPXCHG8B instruction present on most post-80486 processors. Similar toCMPXCHG8B,CMPXCHG16B allows foratomic operations on octa-words (128-bit values). This is useful for parallel algorithms that usecompare and swap on data larger than the size of a pointer, common inlock-free and wait-free algorithms. WithoutCMPXCHG16B one must use workarounds, such as acritical section or alternative lock-free approaches.[60] Its absence also prevents 64-bitWindows prior to Windows 8.1 from having auser-mode address space larger than 8 TiB.[61] The 64-bit version ofWindows 8.1 requires the instruction.[62]LAHF andSAHF instructions in 64-bit mode. AMD introduced these instructions (also in 64-bit mode) with their90 nm (revision D) processors, starting with Athlon 64 in October 2004.[63][64] Intel introduced the instructions in October 2005 with the 0F47h and later revisions ofNetBurst.[70] The 64-bit version of Windows 8.1 requires this feature.[62]BSF andBSR instructions will, when given a source value of 0, leave their destination register unmodified. This is mostly the case on Intel 64 processors as well, except that on some older Intel 64 CPUs, executing these instructions with an operand size of 32 bits will clear the top 32 bits of their destination register even with a source value of 0 (with the low 32 bits kept unchanged.)[80]CLFLUSH is ordered with respect toSFENCE - this is also the case on newer AMD64 processors (Zen 1 and later). On older AMD64 processors, imposing ordering on theCLFLUSH instruction instead requiredMFENCE.
Insupercomputers tracked byTOP500, the appearance of 64-bit extensions for the x86 architecture enabled 64-bit x86 processors by AMD and Intel to replace most RISC processor architectures previously used in such systems (includingPA-RISC,SPARC,Alpha and others), as well as 32-bit x86, even though Intel itself initially tried unsuccessfully to replace x86 with a new incompatible 64-bit architecture in theItanium processor.
As of 2023[update], aHPEEPYC-based supercomputer calledFrontier is number one. The first ARM-based supercomputer appeared on the list in 2018[85] and, in recent years, non-CPU architecture co-processors (GPGPU) have also played a big role in performance. Intel'sXeon Phi "Knights Corner" coprocessors, which implement a subset of x86-64 with some vector extensions,[86] are also used, along with x86-64 processors, in theTianhe-2 supercomputer.[87]
The following operating systems and releases support the x86-64 architecture inlong mode.
Preliminary infrastructure work was started in February 2004 for a x86-64 port.[88] This development later stalled. Development started again during July 2007[89]and continued duringGoogle Summer of Code 2008 and SoC 2009.[90][91] The first official release to contain x86-64 support was version 2.4.[92]
FreeBSD first added x86-64 support under the name "amd64" as an experimental architecture in 5.1-RELEASE in June 2003. It was included as a standard distribution architecture as of 5.2-RELEASE in January 2004. Since then, FreeBSD has designated it as a Tier 1 platform. The 6.0-RELEASE version cleaned up some quirks with running x86 executables under amd64, and most drivers work just as they do on the x86 architecture. Work is currently being done to integrate more fully the x86application binary interface (ABI), in the same manner as the Linux 32-bit ABI compatibility currently works.
x86-64 architecture support was first committed to theNetBSD source tree on June 19, 2001. As of NetBSD 2.0, released on December 9, 2004,NetBSD/amd64 is a fully integrated and supported port.32-bit code is still supported in 64-bit mode, with a netbsd-32 kernel compatibility layer for 32-bit syscalls. The NX bit is used to provide non-executable stack and heap with per-page granularity (segment granularity being used on 32-bit x86).
OpenBSD has supported AMD64 since OpenBSD 3.5, released on May 1, 2004. Complete in-tree implementation of AMD64 support was achieved prior to the hardware's initial release because AMD had loaned several machines for the project'shackathon that year. OpenBSD developers have taken to the platform because of its support for theNX bit, which allowed for an easy implementation of theW^X feature.
The code for the AMD64 port of OpenBSD also runs on Intel 64 processors which contains cloned use of the AMD64 extensions, but since Intel left out the page table NX bit in early Intel 64 processors, there is no W^X capability on those Intel CPUs; later Intel 64 processors added the NX bit under the name "XD bit".Symmetric multiprocessing (SMP) works on OpenBSD's AMD64 port, starting with release 3.6 on November 1, 2004.
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It is possible to enterlong mode underDOS without a DOS extender,[93] but the user must return to real mode in order to call BIOS or DOS interrupts.
It may also be possible to enterlong mode with aDOS extender similar toDOS/4GW, but more complex since x86-64 lacksvirtual 8086 mode. DOS itself is not aware of that, and no benefits should be expected unless running DOS in an emulation with an adequate virtualization driver backend, for example: the mass storage interface.
Linux was the first operating system kernel to run the x86-64 architecture inlong mode, starting with the 2.4 version in 2001 (preceding the hardware's availability).[94][95] Linux also provides backward compatibility for running 32-bit executables. This permits programs to be recompiled into long mode while retaining the use of 32-bit programs. Current Linux distributions ship with x86-64-native kernels anduserlands. Some, such asArch Linux,[96]SUSE,Mandriva, andDebian, allow users to install a set of 32-bit components and libraries when installing off a 64-bit distribution medium, thus allowing most existing 32-bit applications to run alongside the 64-bit OS.
x32 ABI (Application Binary Interface), introduced in Linux 3.4, allows programs compiled for the x32 ABI to run in the 64-bit mode of x86-64 while only using 32-bit pointers and data fields.[97][98][99]Though this limits the program to a virtual address space of 4 GiB, it also decreases the memory footprint of the program and in some cases can allow it to run faster.[97][98][99]
64-bit Linux allows up to 128 TiB of virtual address space for individual processes, and can address approximately 64 TiB of physical memory, subject to processor and system limitations,[100] or up to 128 PiB (virtual) and 4 PiB (physical) with 5-level paging enabled.[101]
Mac OS X 10.4.7 and higher versions ofMac OS X 10.4 run 64-bit command-line tools using the POSIX and math libraries on 64-bit Intel-based machines, just as all versions of Mac OS X 10.4 and 10.5 run them on 64-bit PowerPC machines. No other libraries or frameworks work with 64-bit applications in Mac OS X 10.4.[102]The kernel, and all kernel extensions, are 32-bit only.
Mac OS X 10.5 supports 64-bit GUI applications usingCocoa,Quartz,OpenGL, andX11 on 64-bit Intel-based machines, as well as on 64-bitPowerPC machines.[103]All non-GUI libraries and frameworks also support 64-bit applications on those platforms. The kernel, and all kernel extensions, are 32-bit only.
Mac OS X 10.6 is the first version ofmacOS that supports a 64-bitkernel. However, not all 64-bit computers can run the 64-bit kernel, and not all 64-bit computers that can run the 64-bit kernel will do so by default.[104]The 64-bit kernel, like the 32-bit kernel, supports 32-bit applications; both kernels also support 64-bit applications. 32-bit applications have a virtual address space limit of 4 GiB under either kernel.[105][106] The 64-bit kernel does not support 32-bitkernel extensions, and the 32-bit kernel does not support 64-bit kernel extensions.
OS X 10.8 includes only the 64-bit kernel, but continues to support 32-bit applications; it does not support 32-bit kernel extensions, however.
macOS 10.15 includes only the 64-bit kernel and no longer supports 32-bit applications. This removal of support has presented a problem forWine (and the commercial versionCrossOver), as it needs to still be able to run 32-bit Windows applications. The solution, termedwine32on64, was to addthunks that bring the CPU in and out of 32-bit compatibility mode in the nominally 64-bit application.[107][108]
macOS uses theuniversal binary format to package 32- and 64-bit versions of application and library code into a single file; the most appropriate version is automatically selected at load time. In Mac OS X 10.6, the universal binary format is also used for the kernel and for those kernel extensions that support both 32-bit and 64-bit kernels.
Solaris 10 and later releases support the x86-64 architecture.
For Solaris 10, just as with theSPARC architecture, there is only one operating system image, which contains a 32-bit kernel and a 64-bit kernel; this is labeled as the "x64/x86" DVD-ROM image. The default behavior is to boot a 64-bit kernel, allowing both 64-bit and existing or new 32-bit executables to be run. A 32-bit kernel can also be manually selected, in which case only 32-bit executables will run. Theisainfo command can be used to determine if a system is running a 64-bit kernel.
For Solaris 11, only the 64-bit kernel is provided. However, the 64-bit kernel supports both 32- and 64-bit executables, libraries, and system calls.
x64 editions of Microsoft Windows client and server—Windows XP Professional x64 Edition andWindows Server 2003 x64 Edition—were released in March 2005.[109] Internally they are actually the same build (5.2.3790.1830 SP1),[110][111] as they share the same source base and operating system binaries, so even system updates are released in unified packages, much in the manner as Windows 2000 Professional and Server editions for x86.Windows Vista, which also has many different editions, was released in January 2007.Windows 7 was released in July 2009.Windows Server 2008 R2 was sold in only x64 and Itanium editions; later versions of Windows Server only offer an x64 edition.
Versions of Windows for x64 prior to Windows 8.1 and Windows Server 2012 R2 offer the following:
CMPXCHG16B instruction.[115]Under Windows 8.1 and Windows Server 2012 R2, both user mode and kernel mode virtual address spaces have been extended to 128 TiB.[23] These versions of Windows will not install on processors that lack theCMPXCHG16B instruction.
The following additional characteristics apply to all x64 versions of Windows:
.exe programs) and dynamic link libraries (.dlls) usingWoW64 if WoW64 is supported on that version. Furthermore, a 32-bit program, if it was linked with the "large address aware" option,[112] can use up to 4 GiB of virtual address space in 64-bit Windows, instead of the default 2 GiB (optional 3 GiB with/3GB boot option and "large address aware" link option) offered by 32-bit Windows.[116] Unlike the use of the/3GB boot option on x86, this does not reduce the kernel mode virtual address space available to the operating system. 32-bit applications can, therefore, benefit from running on x64 Windows even if they are not recompiled for x86-64.GS:0 is the address of the first member of the Thread Information Block. Maintaining this convention made the x86-64 port easier, but required AMD to retain the function of the FS and GS segments in long mode – even though segmented addressingper se is not really used by any modern operating system.[113]PREFETCH andPREFETCHW instructions,[118] which are also supported on Intel processors as ofBroadwell.)ThePlayStation 4 andXbox One use AMD x86-64 processors based on theJaguarmicroarchitecture.[122][123] Firmware and games are written in x86-64 code; no legacy x86 code is involved. ThePlayStation 5 andXbox Series X/S use AMD x86-64 processors based on theZen 2 microarchitecture.[124][125] TheSteam Deck uses a custom AMD x86-64accelerated processing unit (APU) based on the Zen 2 microarchitecture.[126]
Since AMD64 and Intel 64 are substantially similar, many software and hardware products use one vendor-neutral term to indicate their compatibility with both implementations. AMD's original designation for this processor architecture, "x86-64", is still used for this purpose,[2] as is the variant "x86_64".[3][4] Other companies, such asMicrosoft[6] andSun Microsystems/Oracle Corporation,[5] use the contraction "x64" in marketing material.
The termIA-64 refers to theItanium processor, and should not be confused with x86-64, as it is a completely different instruction set.
Many operating systems and products, especially those that introduced x86-64 support prior to Intel's entry into the market, use the term "AMD64" or "amd64" to refer to both AMD64 and Intel 64.
arch[3] and in their developer documentation.[2][4]x86-64/AMD64 was solely developed by AMD. Until April 2021 when the relevant patents expired, AMD held patents on techniques used in AMD64;[129][130][131] those patents had to be licensed from AMD in order to implement AMD64. Intel entered into a cross-licensing agreement with AMD, licensing to AMD their patents on existing x86 techniques, and licensing from AMD their patents on techniques used in x86-64.[132] In 2009, AMD and Intel settled several lawsuits and cross-licensing disagreements, extending their cross-licensing agreements.[133][134][135]
arch(1) – Darwin andmacOS General CommandsManualThe kernel and developer tools have standardized on "x86_64" for the name of the Mach-O architecture
Figures 5, 6 and 7 also show the 32-bit version of WAS runs applications at full native hardware performance on the POWER and x86-64 platforms. Unlike some 64-bit processor architectures, the POWER and x86-64 hardware does not emulate 32-bit mode. Therefore applications that do not benefit from 64-bit features can run with full performance on the 32-bit version of WebSphere running on the above mentioned 64-bit platforms.
Physical address space increased to 48 bits.
Physical address space increased to 48 bits
PREFETCHW instruction on page 283.Archived on 29 Dec 2024.To install a 64-bit OS on a 64-bit PC, your processor needs to support CMPXCHG16b, PrefetchW, and LAHF/SAHF.
Intel 64 architecture increases the linear address space for software to 64 bits and supports physical address space up to 46 bits.
BSF andBSR instructions on pages 227 and 229 (footnote 1).Archived on 1 Jan 2025.Status: The kernel, compiler, tool chain work. The kernel boots and work on simulator and is used for porting of userland and running programs
This was the original paper describing the Linux x86-64 kernel port back when x86-64 was only available on simulators.
You can either use the multilib packages or a i686 chroot.
The /LARGEADDRESSAWARE option tells the linker that the application can handle addresses larger than 2 gigabytes.