VIA PadLock is acentral processing unit (CPU)instruction set extension to thex86microprocessorinstruction set architecture (ISA) found on processors produced byVIA Technologies andZhaoxin. Introduced in 2003 with theVIA Centaur CPUs, the additional instructions provide hardware-acceleratedrandom number generation (RNG),Advanced Encryption Standard (AES),SHA-1,SHA256, andMontgomery modular multiplication.[1][2]
The PadLock instruction set can be divided into four subsets:[1]
XSTORE: Store Available Random Bytes (akaXSTORERNG)REP XSTORE: Store ECX Random BytesREP XCRYPTECB:Electronic code bookREP XCRYPTCBC:Cipher Block ChainingREP XCRYPTCTR: Counter Mode (ACE2)REP XCRYPTCFB: Cipher Feedback ModeREP XCRYPTOFB: Output Feedback ModeREP XSHA1: Hash Function SHA-1REP XSHA256: Hash Function SHA-256REP MONTMULThe padlock capability is indicated via aCPUID instruction withEAX = 0xC0000000. If the resultantEAX >= 0xC0000001, the CPU is aware of Centaur features. An additional request withEAX = 0xC0000001 then returns PadLock support inEDX. The padlock capability can be toggled on or off withMSR 0X1107.[1]
VIA PadLock found on someZhaoxin CPUs haveSM3 hashing andSM4 block cipher added.[3]
padlock(4) – FreeBSD Kernel InterfacesManual