The C7 delivers a number of improvements to the olderVIA C3 cores but is nearly identical to the latest VIA C3 Nehemiah core. The C7 was officially launched in May 2005, although according to market reports, full volume production was not in place at that date. In May 2006 Intel'scross-licensing agreement with VIA expired and was not renewed, which was the reason for the forced termination of C3 shipments on March 31, 2006, as VIA lost rights to theSocket 370.
EPIA PX10000G Pico-ITX Motherboard
A 1 GHz C7 processor with 128kB of cache memory is used in VIA's own PX10000Gmotherboard which is based on the proprietaryPico-ITX form factor. The chip is cooled by a large heatsink that covers most of the board and a small 40mm fan.
In early April 2008 the schoolroom-use oriented, ultra-portableHP 2133 Mini-Note PC family debuted with an entirely VIA-based, 1.0, 1.2 and 1.6 GHz C7-M processor portfolio, where the lowest speed model is optimized for running anSSD-based 4GBLinux distribution with a sub $500 price tag, while the middle tier carriesWindows XP and the top model comes withWindows Vista Business, factory default. HP chose the single-core VIA C7-M CPU in order to meet the already fixed $499 starting price, even though Intel's competing Atom processor line debuted on 2 April 2008.
L2 cache increased from 64k to 128k, with associativity increased from 16-way set associative in C3 to 32-way set associative in C7.
VIA has stated[2] the C7 bus is physically based upon the Pentium-M 479-pin packaging, but uses the proprietary VIA V4 bus for electrical signalling, instead of Intel’s AGTL+ Quad Pumped Bus, avoiding legal infringement.
"Twin Turbo" technology, which consists of dualPLLs, one set at a high clock speed, and the other set at a lower speed. This allows the processor's clock frequency to be adjusted in a single processor cycle. Lower switching latency means that more aggressive regulation can be employed.
C7 Esther as an evolutionary step after C3 Nehemiah, in which VIA / Centaur followed their traditional approach of balancing performance against a constrained transistor / power budget.
The cornerstone of the C3 series chips' design philosophy has been that even a relatively simple in-order scalar core can offer reasonable performance against a complex superscalar out-of-order core if supported by an efficient "front-end", i.e. prefetch, cache andbranch prediction mechanisms.
In the case of C7, the design team have focused on further streamlining the (front-end) of the chip, i.e. cache size, associativity and throughput as well as the prefetch system.[3] At the same time no significant changes to the execution core (back-end) of the chip.
The C7 successfully further closes the gap in performance with AMD / Intel chips, since clock speed is not thermally constrained.[citation needed]
