Unified Video Decoder (UVD, previously calledUniversal Video Decoder) is the name given toAMD's dedicatedvideo decodingASIC. There are multiple versions implementing a multitude ofvideo codecs, such asH.264 andVC-1.

UVD was introduced with theRadeon HD 2000 Series and is integrated into some of AMD'sGPUs andAPUs. UVD occupies a considerable amount of thedie surface at the time of its introduction^[1] and is not to be confused with AMD'sVideo Coding Engine (VCE).

As ofAMD Raven Ridge (released January 2018), UVD and VCE were succeeded byVideo Core Next (VCN).

The UVD is based on an ATIXilleon video processor, which is incorporated onto the same die as theGPU and is part of theATI Avivo HD for hardware video decoding, along with the Advanced Video Processor (AVP). UVD, as stated by AMD, handles decoding of H.264/AVC, and VC-1 video codecs entirely in hardware.

The UVD technology is based on theCadence Tensilica Xtensa^[2] processor,^[3][4][5] which was originally licensed by ATI Technologies Inc. in 2004.^[6]

In early versions of UVD,video post-processing is passed to the pixel shaders and OpenCL kernels. MPEG-2 decoding is not performed within UVD, but in the shader processors. The decoder meets the performance and profile requirements ofBlu-ray andHD DVD, decoding H.264 bitstreams up to abitrate of 40 Mbit/s. It hascontext-adaptive binary arithmetic coding (CABAC) support for H.264/AVC.

Unlike video acceleration blocks in previous generation GPUs, which demanded considerable host-CPU involvement, UVD offloads the entire video-decoder process for VC-1 and H.264 except forvideo post-processing, which is offloaded to the shaders. MPEG-2 decode is also supported, but the bitstream/entropy decode is not performed for MPEG-2 video in hardware.

Previously, neither ATIRadeon R520 series'ATI Avivo nor NVidia Geforce 7 series'PureVideo assisted front-end bitstream/entropy decompression in VC-1 and H.264 - the host CPU performed this work.^[7] UVD handlesVLC/CAVLC/CABAC,frequency transform, pixel prediction andinloop deblocking, but passes the post processing to the shaders.^[8] Post-processing includesdenoising, de-interlacing, and scaling/resizing. AMD has also stated that the UVD component being incorporated into the GPU core only occupies 4.7 mm² in area on65 nm fabrication process node.

A variation on UVD, called UVD+, was introduced with theRadeon HD 3000 series. UVD+ supportHDCP for higher resolution video streams.^[9] But UVD+ was also being marketed as simply UVD.

The UVD saw a refresh with the release of theRadeon HD 4000 series products. The UVD 2 features full bitstream decoding of H.264/MPEG-4 AVC, VC-1, as well as iDCT level acceleration of MPEG2 video streams. Performance improvements allow dual video stream decoding andPicture-in-Picture mode. This makes UVD2 fullBD-Live compliant.

The UVD 2.2 features a re-designed local memory interface and enhances the compatibility with MPEG2/H.264/VC-1 videos. However, it was marketed under the same alias as "UVD 2 Enhanced" as the "special core-logic, available in RV770 and RV730 series of GPUs, for hardware decoding of MPEG2, H.264 and VC-1 video with dual-stream decoding". The nature of UVD 2.2 being an incremental update to the UVD 2 can be accounted for this move.

UVD 3 adds support for additional hardware MPEG2 decoding (entropy decode),DivX andXvid viaMPEG-4 Part 2 decoding (entropy decode, inverse transform, motion compensation) andBlu-ray 3D viaMVC (entropy decode, inverse transform, motion compensation, in-loop deblocking).^[10][11] along with 120 Hz stereo 3D support,^[12] and is optimized to utilize less CPU processing power.UVD 3 also adds support for Blu-ray 3D stereoscopic displays.^{[citation needed]}

UVD 4 includes improved frame interpolation with H.264 decoder.^[13] UVD 4.2 was introduced with the AMD Radeon Rx 200 series and Kaveri APU."X.ORG Radeon UVD (Unified Video Decoder) Hardware-UVD4.2: KAVERI, KABINI, MULLINS, BONAIRE, HAWAII". May 2016.

UVD 5 was introduced with the AMD Radeon R9 285. New to UVD is full support for 4K H.264 video, up to level 5.2 (4Kp60).^[14]

The UVD 6.0 decoder andVideo Coding Engine 3.0 encoder were reported to be first used in GPUs based on GCN 3, including Radeon R9 Fury series,^[15][16] followed byAMD Radeon Rx 300 Series (Pirate Islands GPU family) andAMD Radeon Rx 400 Series (Arctic Islands GPU family).^[17] The UVD version in "Fiji" and "Carrizo"-based graphics controller hardware is also announced to provide support forHigh Efficiency Video Coding (HEVC, H.265) hardware video decoding, up to 4K, 8-bits color (H.265 version 1, main profile);^[18][19][20] and there is support for the10bit-color HDR both H.265 andVP9 video codec in the AMD Radeon 400 series with UVD 6.3.^[21][22][23]

The UVD 7.0 decoder andVideo Coding Engine 4.0 encoder are included in the Vega-based GPUs.^[24][25] But there is still no fixed function VP9 hardware decoding.^[26]

AMD's Vega20 GPU, present in the Instinct Mi50, Instinct Mi60 and Radeon VII cards, include VCE 4.1 and two UVD 7.2 instances.^[27][28]

Starting with the integrated graphics of the Raven Ridge APU (Ryzen 2200/2400G), the former UVD and VCE have been replaced by the new "Video Core Next" (VCN). VCN 1.0 adds full hardware decoding for the VP9 codec.^[29]

^[30][29]

Most of theRadeon HD 2000 seriesvideo cards implement the UVD for hardware decoding of 1080p high definition contents.^[31] However, the Radeon HD 2900 series video cards do not include the UVD (though it is able to provide partial functionality through the use of its shaders), which was incorrectly stated to be present on the product pages and package boxes of the add-in partners' products before the launch of the Radeon HD 2900 XT,^{[citation needed]} either stating the card as featuring ATI Avivo HD or explicitly UVD,^{[citation needed]} which only the former statement of ATI Avivo HD is correct. The exclusion of UVD was also confirmed by AMD officials.^[32]

UVD2 is implemented in theRadeon RV7x0 and R7x0 series GPUs. This also includes the RS7x0 series used for theAMD 700 chipset seriesIGP motherboards.

The following table shows features ofAMD's processors with 3D graphics, includingAPUs (see also:List of AMD processors with 3D graphics).

Platform			High, standard and low power														Low and ultra-low power
Codename	Server	Basic						Toronto
		Micro																Kyoto
	Desktop	Performance													Raphael	Phoenix
		Mainstream	Llano	Trinity	Richland	Kaveri	Kaveri Refresh (Godavari)	Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir	Cezanne
		Entry
		Basic																Kabini				Dalí
	Mobile	Performance										Renoir	Cezanne	Rembrandt	Dragon Range
		Mainstream	Llano	Trinity	Richland	Kaveri		Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir Lucienne	Cezanne Barceló			Phoenix
		Entry																				Dalí			Mendocino
		Basic															Desna, Ontario, Zacate	Kabini, Temash	Beema, Mullins	Carrizo-L	Stoney Ridge		Pollock
	Embedded			Trinity		Bald Eagle		Merlin Falcon, Brown Falcon		Great Horned Owl		Grey Hawk					Ontario, Zacate	Kabini	Steppe Eagle,Crowned Eagle, LX-Family		Prairie Falcon	Banded Kestrel		River Hawk
Released			Aug 2011	Oct 2012	Jun 2013	Jan 2014	2015	Jun 2015	Jun 2016	Oct 2017	Jan 2019	Mar 2020	Jan 2021	Jan 2022	Sep 2022	Jan 2023	Jan 2011	May 2013	Apr 2014	May 2015	Feb 2016	Apr 2019	Jul 2020	Jun 2022	Nov 2022
CPUmicroarchitecture			K10	Piledriver		Steamroller		Excavator	"Excavator+"[33]	Zen	Zen+	Zen 2	Zen 3	Zen 3+	Zen 4		Bobcat	Jaguar	Puma	Puma+[34]	"Excavator+"	Zen		Zen+	"Zen 2+"
ISA			x86-64 v1	x86-64 v2				x86-64 v3							x86-64 v4		x86-64 v1	x86-64 v2			x86-64 v3
Socket	Desktop	Performance	—												AM5	—	—
		Mainstream	—					AM4						—		—
		Entry	FM1	FM2		FM2+		FM2+[a],AM4	AM4					—
		Basic	—														—	AM1	—			FP5	—
	Other		FS1	FS1+,FP2		FP3		FP4		FP5		FP6		FP7	FL1	FP7 FP7r2 FP8	FT1	FT3	FT3b		FP4	FP5	FT5	FP5	FT6
PCI Express version			2.0			3.0								4.0	5.0	4.0	2.0				3.0
CXL			—														—
Fab. (nm)			GF32SHP (HKMGSOI)			GF28SHP (HKMG bulk)				GF14LPP (FinFET bulk)	GF12LP (FinFET bulk)	TSMCN7 (FinFET bulk)		TSMCN6 (FinFET bulk)	CCD: TSMCN5 (FinFET bulk) cIOD: TSMCN6 (FinFET bulk)	TSMC4nm (FinFET bulk)	TSMCN40 (bulk)	TSMCN28 (HKMG bulk)	GF 28SHP (HKMG bulk)			GF14LPP (FinFET bulk)		GF12LP (FinFET bulk)	TSMCN6 (FinFET bulk)
Die area (mm2)			228	246		245		245	250	210[35]		156	180	210	CCD: (2x) 70 cIOD: 122	178	75(+ 28FCH)	107		?	125	149			~100
MinTDP (W)			35	17				12				10		15	65	35	4.5	4	3.95	10	6			12	8
Max APUTDP (W)			100			95		65						45	170	54	18	25					6	54	15
Max stock APU base clock (GHz)			3	3.8	4.1	4.1		3.7	3.8	3.6	3.7	3.8	4.0	3.3	4.7	4.3	1.75	2.2	2	2.2	3.2	2.6	1.2	3.35	2.8
Max APUs per node[b]			1														1
Max core dies per CPU			1												2	1	1
Max CCX per core die			1									2	1				1
Max cores per CCX			4										8				2	4			2			4
MaxCPU[c]cores per APU			4									8			16	8	2	4			2			4
Maxthreads per CPU core			1							2							1					2
Integer pipeline structure			3+3	2+2						4+2		4+2+1	1+3+3+1+2				1+1+1+1				2+2	4+2			4+2+1
i386, i486, i586, CMOV, NOPL, i686,PAE,NX bit, CMPXCHG16B,AMD-V,RVI,ABM, and 64-bit LAHF/SAHF
IOMMU[d]			—	v2													v1		v2
BMI1,AES-NI,CLMUL, andF16C																	—
MOVBE			—
AVIC,BMI2,RDRAND, and MWAITX/MONITORX																	—
SME[e],TSME[e],ADX,SHA,RDSEED,SMAP,SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing			—														—
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT			—														—
MPK,VAES			—														—
SGX			—														—
FPUs percore			1	0.5						1							1				0.5	1
Pipes per FPU			2														2
FPU pipe width			128-bit									256-bit					80-bit	128-bit							256-bit
CPUinstruction setSIMD level			SSE4a[f]	AVX				AVX2							AVX-512		SSSE3	AVX			AVX2
3DNow!			3DNow!+	—													—
PREFETCH/PREFETCHW
GFNI			—														—
AMX			—
FMA4, LWP,TBM, andXOP			—							—							—					—
FMA3
AMD XDNA			—														—
L1 data cache per core (KiB)			64	16				32									32
L1 data cacheassociativity (ways)			2	4				8									8
L1 instruction caches percore			1	0.5						1							1				0.5	1
Max APU total L1 instruction cache (KiB)			256	128		192				256					512	256	64		128		96	128
L1 instruction cacheassociativity (ways)			2			3				4		8					2				3	4			8
L2 caches percore			1	0.5						1							1				0.5	1
Max APU total L2 cache (MiB)			4					2				4			16		1	2			1			2
L2 cacheassociativity (ways)			16							8							16					8
Max on-dieL3 cache per CCX (MiB)			—							4			16		32		—						4
Max 3D V-Cache per CCD (MiB)										—					64	—							—
Max total in-CCDL3 cache per APU (MiB)										4		8	16		64								4
Max. total 3D V-Cache per APU (MiB)										—					64	—							—
Max. boardL3 cache per APU (MiB)										—													—
Max totalL3 cache per APU (MiB)										4		8	16		128								4
APU L3 cacheassociativity (ways)										16													16
L3 cache scheme										Victim													Victim
Max.L4 cache			—														—
Max stockDRAM support			DDR3-1866		DDR3-2133			DDR3-2133,DDR4-2400	DDR4-2400	DDR4-2933		DDR4-3200,LPDDR4-4266		DDR5-4800,LPDDR5-6400	DDR5-5200	DDR5-5600,LPDDR5x-7500	DDR3L-1333	DDR3L-1600	DDR3L-1866		DDR3-1866,DDR4-2400	DDR4-2400	DDR4-1600	DDR4-3200	LPDDR5-5500
MaxDRAM channels per APU			2														1					2	1	2
Max stockDRAMbandwidth (GB/s) per APU			29.866		34.132			38.400		46.932		68.256		102.400	83.200	120.000	10.666	12.800	14.933		19.200	38.400	12.800	51.200	88.000
GPUmicroarchitecture			TeraScale 2 (VLIW5)	TeraScale 3 (VLIW4)		GCN 2nd gen		GCN 3rd gen		GCN 5th gen[36]				RDNA 2		RDNA 3	TeraScale 2 (VLIW5)	GCN 2nd gen			GCN 3rd gen[36]	GCN 5th gen			RDNA 2
GPUinstruction set			TeraScale instruction set			GCN instruction set								RDNA instruction set			TeraScale instruction set	GCN instruction set							RDNA instruction set
Max stock GPU base clock (MHz)			600	800	844	866		1108		1250	1400	2100		2400	400		538	600	?	847	900	1200	600	1300	1900
Max stock GPU baseGFLOPS[g]			480	614.4	648.1	886.7		1134.5		1760	1971.2	2150.4		3686.4	102.4		86	?	?	?	345.6	460.8	230.4	1331.2	486.4
3D engine[h]			Up to 400:20:8	Up to 384:24:6		Up to 512:32:8				Up to 704:44:16[37]		Up to 512:32:8		768:48:8	128:8:4		80:8:4	128:8:4			Up to 192:12:8	Up to 192:12:4	192:12:4	Up to 512:?:?	128:?:?
			IOMMUv1			IOMMUv2											IOMMUv1		?		IOMMUv2
Video decoder			UVD 3.0			UVD 4.2		UVD 6.0		VCN 1.0[38]		VCN 2.1[39]	VCN 2.2[39]	VCN 3.1		?	UVD 3.0	UVD 4.0	UVD 4.2		UVD 6.2	VCN 1.0			VCN 3.1
Video encoder			—	VCE 1.0		VCE 2.0		VCE 3.1									—	VCE 2.0			VCE 3.4
AMD Fluid Motion
GPU power saving			PowerPlay	PowerTune													PowerPlay	PowerTune[40]
TrueAudio			—			[41]							?				—
FreeSync						1 2												1 2
HDCP[i]			?			1.4				2.2				2.3			?	1.4				2.2			2.3
PlayReady[i]			—							3.0 not yet							—					3.0 not yet
Supported displays[j]			2–3	2–4				3		3 (desktop) 4 (mobile, embedded)		4					2				3	4		4
/drm/radeon[k][43][44]									—												—
/drm/amdgpu[k][45]			—			[46]											—	[46]

The following table shows features ofAMD/ATI'sGPUs (see also:List of AMD graphics processing units).

Name ofGPU series	Wonder	Mach	3D Rage	Rage Pro	Rage 128	R100	R200	R300	R400	R500	R600	RV670	R700	Evergreen	Northern Islands		Southern Islands	Sea Islands	Volcanic Islands	Arctic Islands/Polaris	Vega	Navi 1x	Navi 2x	Navi 3x	Navi 4x
Released	1986	1991	Apr 1996	Mar 1997	Aug 1998	Apr 2000	Aug 2001	Sep 2002	May 2004	Oct 2005	May 2007	Nov 2007	Jun 2008	Sep 2009	Oct 2010	Dec 2010	Jan 2012	Sep 2013	Jun 2015	Jun 2016, Apr 2017, Aug 2019	Jun 2017, Feb 2019	Jul 2019	Nov 2020	Dec 2022	Feb 2025
Marketing Name	Wonder	Mach	3D Rage	Rage Pro	Rage 128	Radeon 7000	Radeon 8000	Radeon 9000	Radeon X700/X800	Radeon X1000	Radeon HD 2000	Radeon HD 3000	Radeon HD 4000	Radeon HD 5000	Radeon HD 6000		Radeon HD 7000	Radeon 200	Radeon 300	Radeon 400/500/600	Radeon RX Vega, Radeon VII	Radeon RX 5000	Radeon RX 6000	Radeon RX 7000	Radeon RX 9000
AMD support
Kind	2D		3D
Instruction set architecture	Not publicly known										TeraScale instruction set						GCN instruction set					RDNA instruction set
Microarchitecture	Not publicly known					GFX1		GFX2			TeraScale 1 (VLIW5) (GFX3)			TeraScale 2 (VLIW5) (GFX4)	TeraScale 2 (VLIW5) up to 68xx (GFX4)	TeraScale 3 (VLIW4) in 69xx[47][48] (GFX5)	GCN 1st gen (GFX6)	GCN 2nd gen (GFX7)	GCN 3rd gen (GFX8)	GCN 4th gen (GFX8)	GCN 5th gen (GFX9)	RDNA (GFX10.1)	RDNA 2 (GFX10.3)	RDNA 3 (GFX11)	RDNA 4 (GFX12)
Type	Fixed pipeline[a]						Programmable pixel & vertex pipelines				Unified shader model
Direct3D	—		5.0	6.0		7.0	8.1	9.0 11 (9_2)	9.0b 11 (9_2)	9.0c 11 (9_3)	10.0 11 (10_0)	10.1 11 (10_1)		11 (11_0)			11 (11_1) 12 (11_1)	11 (12_0) 12 (12_0)			11 (12_1) 12 (12_1)		11 (12_1) 12 (12_2)
Shader model	—						1.4	2.0+	2.0b	3.0	4.0	4.1		5.0			5.1	5.1 6.5			6.7				6.8
OpenGL	—			1.1	1.2	1.3		1.5[b][49]			3.3			4.6[50][c]
Vulkan	—															1.1[c][d]	1.3[51][e]		1.4[52]
OpenCL	—										Close to Metal		1.1 (not supported byMesa)	1.2+ (onLinux: 1.1+ (no Image support on Clover, with by Rusticl) with Mesa, 1.2+ on GCN 1.Gen)				2.0+ (Adrenalin driver onWin7+) (onLinux ROCm, Mesa 1.2+ (no Image support in Clover, but in Rusticl with Mesa, 2.0+ and 3.0 with AMD drivers or AMD ROCm), 5th gen: 2.2 win 10+ and Linux RocM 5.0+				2.2+ and 3.0 Windows 8.1+ and Linux ROCm 5.0+ (Mesa Rusticl 1.2+ and 3.0 (2.1+ and 2.2+ wip))[53][54][55]
HSA /ROCm	—																					?
Video decodingASIC	—										Avivo/UVD	UVD+	UVD 2	UVD 2.2	UVD 3		UVD 4	UVD 4.2	UVD 5.0 or6.0	UVD 6.3	UVD 7[24][f]	VCN 2.0[24][f]	VCN 3.0[56]	VCN 4.0	VCN 5.0
Video encodingASIC	—																VCE 1.0	VCE 2.0	VCE 3.0 or 3.1	VCE 3.4	VCE 4.0[24][f]
Fluid Motion[g]																								?
Power saving	?										PowerPlay				PowerTune		PowerTune &ZeroCore Power					?
TrueAudio	—																	Via dedicatedDSP		Via shaders
FreeSync	—																	1 2
HDCP[h]	—										?							1.4		2.2		2.3[57]
PlayReady[h]	—																			3.0		3.0
Supported displays[i]						1–2	2							2–6								?			4
Max.resolution	?													2–6 × 2560×1600			2–6 × 4096×2160 @ 30 Hz			2–6 × 5120×2880 @ 60 Hz	3 × 7680×4320 @ 60 Hz[58]	7680×4320 @ 60 HzPowerColor		7680x4320 @165 Hz	7680x4320
/drm/radeon[j]																			—
/drm/amdgpu[j]	—																	Optional[59]

The UVD SIP core needs to be supported by thedevice driver, which provides one or moreinterfaces such asVDPAU,VAAPI orDXVA. One of these interfaces is then used by end-user software, for exampleVLC media player orGStreamer, to access the UVD hardware and make use of it.

AMD Catalyst, AMD'sproprietary graphics device driver that supports UVD, is available for Microsoft Windows and some Linux distributions. Additionally, afree device driver is available, which also supports the UVD hardware.

Support for UVD has been available in AMD's proprietary driverCatalyst version 8.10 since October 2008 throughX-Video Motion Compensation (XvMC) orX-Video Bitstream Acceleration (XvBA).^[61][62] Since April 2013,^[63] UVD is supported by thefree and open-source "radeon" device driver throughVideo Decode and Presentation API for Unix (VDPAU). An implementation of VDPAU is available asGallium3D state tracker inMesa 3D.

On 28 June 2014,Phoronix published some benchmarks on using Unified Video Decoder through the VDPAU interface runningMPlayer on Ubuntu 14.04 with version 10.3-testing of Mesa 3D.^[64]

Microsoft Windows supported UVD since it was launched. UVD currently only supportsDXVA (DirectX Video Acceleration)API specification for theMicrosoft Windows andXbox 360 platforms to allowvideodecoding to be hardware accelerated, thus themedia player software also has to support DXVA to be able to utilize UVD hardware acceleration.

Support for running customFreeRTOS-based firmware on the Radeon HD 2400's UVD core (based on an Xtensa CPU), interfaced with a STM32 ARM-based board viaI²C, was attempted as of January 2012.^[65]

TheVideo Shader andATI Avivo are similar technologies incorporated into previous ATI products.

The UVD was succeeded by AMD Video Core Next in the Raven Ridge series of APUs released in October 2017. The VCN combines both encode (VCE) and decode (UVD).^[66]

• PureVideo -Nvidia
• GeForce 256's Motion Compensation
• High-Definition Video Processor
• Video Processing Engine
• Nvidia NVENC
• Nvidia NVDEC

• Video Core Next -AMD
• Video Coding Engine -AMD
• Unified Video Decoder -AMD
• Video Shader -ATI

• Quick Sync Video -Intel
• Clear Video -Intel

• Qualcomm Hexagon

• VDPAU – Video Decode and Presentation API for Unix, from NVIDIA
• Video Acceleration API (VA API) – an alternative video acceleration API to XvBA for Linux/UNIX operating-system that supports XvBA as a backend
• X-Video Bitstream Acceleration (XvBA) – AMD's future hardware acceleration API for Linux/UNIX operating-system.
• Bit stream decoder (BSD)
• Comparison of AMD graphics processing units
• DirectX Video Acceleration (DxVA) – Microsoft's hardware acceleration API forMicrosoft Windows based operating-system.

• ATI Avivo HD Technology Brief, July 2008
• AMD Video Technologies, October 2010
• Presentation slides comparison between CPU decode, ATI Avivo HD and PureVideo HD and Decode comparison of VC-1 and H.264 video
• AMD Media Codecs (an optional download)

• ATI Technologies
• Video acceleration
• AMD IP cores
• Video compression and decompression ASIC

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