Unibus

Unibus
Unibus backplane (left) and twoexpansion cards
Year created	1969; 56 years ago (1969)
Created by	Digital Equipment Corporation
Width in bits	18 address, 16 data
Style	Parallel

TheUnibus was the earliest of several computerbus andbackplane designs used withPDP-11 and earlyVAX systems manufactured by theDigital Equipment Corporation (DEC) ofMaynard,Massachusetts. The Unibus was developed around 1969 byGordon Bell and student Harold McFarland while atCarnegie Mellon University.^[1]

The name refers to the unified nature of the bus; Unibus was used both as asystem bus allowing thecentral processing unit to communicate withmain memory, as well as aperipheral bus, allowing peripherals to send and receive data. Unifying these formerly separate busses allowed external devices to easily performdirect memory access (DMA) and made the construction ofdevice drivers easier as control and data exchange was all handled throughmemory-mapped I/O.^[2]

Unibus was physically large, which led to the introduction ofQ-bus, whichmultiplexed some signals to reduce pin count. Higher performance PDP systems used Fastbus, essentially two Unibusses in one. The system was later supplanted byMassbus, a dedicated I/O bus introduced on theVAX and late-model PDP-11s.

The Unibus consists of 72 signals, usually connected via two 36-wayedge connectors on eachprinted circuit board. When not counting the power and ground lines, it is usually referred to as a 56-line bus. It can exist within abackplane or on a cable. Up to 20 nodes (devices) can be connected to a single Unibus segment; additional segments can be connected via a busrepeater.

The bus is completelyasynchronous, allowing a mixture of fast and slow devices. It allows the overlapping of arbitration (selection of the nextbus master) while the current bus master is still performing data transfers. The 18 address lines allow the addressing of a maximum of 256 KB. Typically, the top 8 KB is reserved for the registers of thememory-mapped I/O devices used in the PDP-11 architecture.

The design deliberately minimizes the amount of redundant logic required in the system. For example, a system always contains more slave devices than master devices so most of the complex logic required to implement asynchronous data transfers is forced into the relatively few master devices. For interrupts, only theinterrupt-fielding processor needs to contain the complex timing logic. The result is that most I/O controllers can be implemented with simple logic, and most of the critical logic is implemented as a customMSI IC.

Type 1 lines are a normal multi-senderwired-OR bus withpull-up resistors at each end of the bus, typically on aterminator card.^[3]

Type 2 lines are selectively propagated by each card to the next slot – if the card wants to keep the request grant it will assert the SACK line and not propagate the request to the next slot. If a slot is empty, it is necessary to install a "grant continuity card" in the slot to propagate the four type 2 signals to the next card.^[3]

Type 3 signals are generated by the power supply and have only a single sender. They warn the devices on the bus when the power is about to fail, so those devices can execute an orderly shutdown, and disable operations to prevent spurious writes.^[3]

The two control lines (C0 and C1) allowed the selection of four different data transfer cycles:

• DATI (Data In, a read)
• DATIP (Data In/Pause, the first portion of a Read-Modify-Write operation. A DATO or DATOB operation completes this.)
• DATO (Data Out, a word write)
• DATOB (Data Out/Byte, a byte write)
• During an interrupt cycle, a fifth style of transfer was automatically invoked to convey aninterrupt vector from the interrupting device to theinterrupt-fielding processor.

• Computer buses
• DEC hardware
• PDP-11
• Computer-related introductions in 1969

• Articles with short description
• Short description matches Wikidata