AMD Turion is thebrand nameAMD applies to itsx86-64 low-power consumptionmobile processors codenamedK8L.[1] The Turion 64 and Turion 64 X2/Ultra processors compete withIntel's mobile processors, initially thePentium M and theIntel Core andIntel Core 2 processors.
EarliestTurion 64 processors are plugged into AMD'sSocket 754. They are equipped with 512 or 1024KiB of L2 cache, a 64-bit single channel on-die DDR-400 memory controller, and an 800 MHzHyperTransport bus. Battery saving features, likePowerNow!, are central to the marketing and usefulness of these CPUs. The newer "Richmond" models are designed for AMD'sSocket S1 and have a double-channel DDR2 controller.
Turion 64 X2 isAMD's64-bitdual-coremobile CPU, intended to compete withIntel'sCore andCore 2 CPUs. The Turion 64 X2 was launched on May 17, 2006,[2] after several delays. These processors useSocket S1 and featureDDR2 memory. They also includeAMD Virtualization Technology and more power-saving features.
The earlier 90 nm devices werecodenamed Taylor and Trinidad, while the newer 65 nm cores have codename Tyler.
Turion X2 Ultra (codenamedGriffin) is the first processor family fromAMD solely for the mobile platform, based on theAthlon 64 (K8 Revision G) architecture with some specific architectural enhancements similar to currentPhenom processors aimed at lower power consumption and longer battery life. The Turion Ultra processor was released as part of the "Puma" mobile platform in June 2008.
The Turion X2 Ultra is a dual-core processor fabricated on65 nm technology using 300 mm SOI wafers. It supportsDDR2-800SO-DIMMs and features a DRAM prefetcher to improve performance and a mobile-enhancednorthbridge (memory controller, HyperTransport controller, and crossbar switch). Each processor core comes with 1MiB L2 cache for a total of 2 MiB L2 cache for the entire processor. This is double the L2 cache found on the Turion 64 X2 processor. Clock rates range from 2.0 GHz to 2.4 GHz, and thermal design power (TDP) range from 32 watts to 35 watts.[3]
The Turion X2 Ultra processor, unlike earlier Turions, implements three voltage planes: one for the northbridge and one for each core.[4] This, along with multiplephase-locked loops (PLL), allows one core to alter its voltage and operating frequency independently of the other core, and independently of the northbridge. Indeed, in a matter of microseconds, the processor can switch to one of 8 frequency levels and one of 5 voltage levels. By adjusting frequency and voltage during use, the processor can adapt to different workloads and help reduce power consumption. It can operate as low as 250 MHz to conserve power during light use.
Additionally, the processor featuresdeep sleep state C3, deeper sleep state C4 (AltVID), andHyperTransport 3.0 up to 2.6 GHz, or up to 41.6GB/s bandwidth per link at 16-bit link width and dynamic scaling of HT link width down to 0-bit ("disconnected") in both directions from and to thechipset for four different usage scenarios.[5] It also implements multiple on-die thermal sensors through integrated SMBUS (SB-TSI) interface (replaces and eliminates the thermal monitor circuit chip through SMBUS in its predecessors) with additional MEMHOT signal sent from embedded controller to the processor, and reduces memory temperature.
The Turion X2 Ultra processor uses the same socket S1 as its predecessor,Turion 64 X2, but the pinout is different.[6] It is designed to work with theRS780M chipset.
Given the above enhancements on the architecture, the cores were minimally modified and are based on the K8 instead of theK10 microarchitecture.[6] AMD Fellow Maurice Steinman has said the cores are almost transistor-for-transistor identical to those found in the 65 nm Turion 64 X2 processors.[citation needed]
Turion II Ultra (codenamedCaspian) is the mobile version of the K10.5 architecture produced using 45 nm fabrication process, also known by its desktop variantRegor. It is a dual core processor, and features clock speeds of 2.5 GHz, 2 MB total L2 cache (1 MB per core), HyperTransport at 3.6 GT/s, and a 128 bit FPU. It maintains a TDP of 35W from its predecessor Turion X2 Ultra (codenamedGriffin).
Turion II is identical to Turion II Ultra, except that the Turion II features only 1 MB of L2 cache (512 KB per core), and lower clock speeds ranging from 2.2 GHz to 2.6 GHz.
The model naming scheme does not make it obvious how to compare one Turion with another, or even anAthlon 64. The model name is two letters, a dash, and a two digit number (for example, ML-34). The two letters together designate a processor class, while the number represents aperformance rating (PR). The first letter is M for mono (single) core processors and T for twin (dual) coreTurion 64 X2 processors. The later in the alphabet that the second letter appears, the more the model has been designed for mobility (frugal power consumption). Take for instance, an MT-30 and an ML-34. Since the T in the MT-30 is later in the alphabet than the L in ML-34, the MT-30 consumes less power than the ML-34. But since 34 is greater than 30, the ML-34 is faster than the MT-30.
The release of the Turion II Ultra and Turion II lineups have simplified name methodology; all newly released Turions have the letter "M" followed by a number designating relative performance. The higher the number, the higher the clock speed. For example, the Turion II M500 has a clock speed of 2.2 GHz while the Turion II M520 has a clock speed of 2.3 GHz.
Code-named | Core | Date released |
---|---|---|
Lancaster Richmond Sable | solo (90 nm) solo (90 nm) solo (65 nm) | Mar 2005 Sep 2006 Jun 2008 |
Taylor Trinidad Tyler Lion | dual (90 nm) dual (90 nm) dual (65 nm) dual (65 nm) | May 2006 May 2006 May 2007 Jun 2008 |
Griffin | dual (65 nm) | Jun 2008 |
Caspian | dual (45 nm) | Sep 2009 |
Champlain | dual (45 nm) | May 2010 |
The models support the same features available in Lancaster, plusAMD-V.
Model number | Frequency | L2 cache | FPU width | HT | Multiplier1 | Voltage | TDP | Socket | Release date | Order part number |
---|---|---|---|---|---|---|---|---|---|---|
Turion II P520 | 2.3 GHz | 2 × 1 MB | 128-bit | 1.8 GHz | 11.5× | 25 W | Socket S1g4 | May 12, 2010 | TMP520SGR23GM | |
Turion II P540 | 2.4 GHz | 2 × 1 MB | 128-bit | 1.8 GHz | 12× | 25 W | Socket S1g4 | October 4, 2010 | TMP540SGR23GM | |
Turion II P560 | 2.5 GHz | 2 × 1 MB | 128-bit | 1.8 GHz | 12.5× | 25 W | Socket S1g4 | October 19, 2010 | TMP560SGR23GM | |
Turion II N530 | 2.5 GHz | 2 × 1 MB | 128-bit | 1.8 GHz | 12.5× | 35 W | Socket S1g4 | May 12, 2010 | TMN530DCR23GM | |
Turion II N550 | 2.6 GHz | 2 × 1 MB | 128-bit | 1.8 GHz | 13× | 35 W | Socket S1g4 | October 4, 2010 | TMN550DCR23GM |