Asystem on a chip orsystem-on-chip (SoC/ˌˈɛsoʊsiː/; pl.SoCs/ˌˈɛsoʊsiːz/) is anintegrated circuit that integrates most or all components of acomputer orelectronic system. These components usually include an on-chipcentral processing unit (CPU),memory interfaces,input/output devices and interfaces, andsecondary storage interfaces, often alongside other components such as aWi-Fi receiver and agraphics processing unit (GPU) – all on a singlesubstrate or microchip.[1] SoCs may containdigital and alsoanalog,mixed-signal and oftenradio frequencysignal processing functions (otherwise it may be considered on a discrete application processor).
High-performance SoCs are often paired with dedicated and physically separate memory and secondary storage (such asLPDDR andeUFS oreMMC, respectively) chips that may be layered on top of the SoC in what is known as apackage on package (PoP) configuration, or be placed close to the SoC. Additionally, SoCs may paired with smaller separate chips, such as basebandmodems.[2]
An SoC usuallyintegrates amicrocontroller,microprocessor or perhaps several processor cores with peripherals like aGPU and aWi-Fi receiver and morecoprocessors. Similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory, an SoC can be seen as integrating a microcontroller with even more advancedperipherals.
Compared to a multi-chip architecture, an SoC with equivalent functionality will have reducedpower consumption as well as a smallersemiconductor die area. This comes at the cost of reducedreplaceability of components. By definition, SoC designs are fully or nearly fully integrated across different componentmodules. For these reasons, there has been a general trend towards tighter integration of components in thecomputer hardware industry, in part due to the influence of SoCs and lessons learned from the mobile and embedded computing markets.
SoCs are very common in themobile computing (as insmart devices such assmartphones andtablet computers) andedge computing markets.[3][4]
In general, there are three distinguishable types of SoCs:
SoCs can be applied to any computing task. However, they are typically used in mobile computing such as tablets, smartphones, smartwatches, and netbooks as well asembedded systems and in applications where previouslymicrocontrollers would be used.
Where previously only microcontrollers could be used, SoCs are rising to prominence in the embedded systems market. Tighter system integration offers better reliability andmean time between failure, and SoCs offer more advanced functionality and computing power than microcontrollers.[5] Applications includeAI acceleration, embeddedmachine vision,[6]data collection,telemetry,vector processing andambient intelligence. Often embedded SoCs target theinternet of things, multimedia, networking, telecommunications andedge computing markets. Some examples of SoCs for embedded applications include STM32, RP2040, and AMD Zynq 7000.
Mobile computing based SoCs always bundle processors, memories, on-chipcaches,wireless networking capabilities and oftendigital camera hardware and firmware. With increasing memory sizes, high end SoCs will often have no memory and flash storage and instead, the memory andflash memory will be placed right next to, or above (package on package), the SoC.[7] Some examples of mobile computing SoCs include:
In 1992,Acorn Computers produced theA3010, A3020 and A4000 range of personal computers with the ARM250 SoC. It combined the original Acorn ARM2 processor with a memory controller (MEMC), video controller (VIDC), and I/O controller (IOC). In previous AcornARM-powered computers, these were four discrete chips. The ARM7500 chip was their second-generation SoC, based on the ARM700, VIDC20 and IOMD controllers, and was widely licensed in embedded devices such as set-top-boxes, as well as later Acorn personal computers.
Tablet and laptop manufacturers have learned lessons from embedded systems and smartphone markets about reduced power consumption, better performance and reliability from tighterintegration of hardware andfirmwaremodules, andLTE and otherwireless network communications integrated on chip (integratednetwork interface controllers).[10]
On modern laptops and mini PCs, the low-power variants ofAMD Ryzen andIntel Core processors use SoC design integrating CPU, IGPU, chipset and other processors in a single package. However, such x86 processors still require external memory and storage chips.
An SoC consists of hardwarefunctional units, includingmicroprocessors that runsoftware code, as well as acommunications subsystem to connect, control, direct and interface between these functional modules.
An SoC must have at least oneprocessor core, but typically an SoC has more than one core. Processor cores can be amicrocontroller,microprocessor (μP),[11]digital signal processor (DSP) orapplication-specific instruction set processor (ASIP) core.[12] ASIPs haveinstruction sets that are customized for anapplication domain and designed to be more efficient than general-purpose instructions for a specific type of workload. Multiprocessor SoCs have more than one processor core by definition. TheARM architecture is a common choice for SoC processor cores because some ARM-architecture cores aresoft processors specified asIP cores.[11]
SoCs must havesemiconductor memory blocks to perform their computation, as domicrocontrollers and otherembedded systems. Depending on the application, SoC memory may form amemory hierarchy andcache hierarchy. In the mobile computing market, this is common, but in manylow-power embedded microcontrollers, this is not necessary. Memory technologies for SoCs includeread-only memory (ROM),random-access memory (RAM), Electrically Erasable Programmable ROM (EEPROM) andflash memory.[11] As in other computer systems, RAM can be subdivided into relatively faster but more expensivestatic RAM (SRAM) and the slower but cheaperdynamic RAM (DRAM). When an SoC has acache hierarchy, SRAM will usually be used to implementprocessor registers and cores'built-in caches whereas DRAM will be used formain memory. "Main memory" may be specific to a single processor (which can bemulti-core) when the SoChas multiple processors, in this case it isdistributed memory and must be sent via§ Intermodule communication on-chip to be accessed by a different processor.[12] For further discussion of multi-processing memory issues, seecache coherence andmemory latency.
SoCs include externalinterfaces, typically forcommunication protocols. These are often based upon industry standards such asUSB,Ethernet,USART,SPI,HDMI,I²C,CSI, etc. These interfaces will differ according to the intended application.Wireless networking protocols such asWi-Fi,Bluetooth,6LoWPAN andnear-field communication may also be supported.
When needed, SoCs includeanalog interfaces includinganalog-to-digital anddigital-to-analog converters, often forsignal processing. These may be able to interface with different types ofsensors oractuators, includingsmart transducers. They may interface with application-specificmodules or shields.[nb 1] Or they may be internal to the SoC, such as if an analog sensor is built in to the SoC and its readings must be converted to digital signals for mathematical processing.
Digital signal processor (DSP) cores are often included on SoCs. They performsignal processing operations in SoCs forsensors,actuators,data collection,data analysis and multimedia processing. DSP cores typically featurevery long instruction word (VLIW) andsingle instruction, multiple data (SIMD)instruction set architectures, and are therefore highly amenable to exploitinginstruction-level parallelism throughparallel processing andsuperscalar execution.[12]: 4 SP cores most often feature application-specific instructions, and as such are typicallyapplication-specific instruction set processors (ASIP). Such application-specific instructions correspond to dedicated hardwarefunctional units that compute those instructions.
Typical DSP instructions includemultiply-accumulate,Fast Fourier transform,fused multiply-add, andconvolutions.
As with other computer systems, SoCs requiretiming sources to generateclock signals, control execution of SoC functions and provide time context tosignal processing applications of the SoC, if needed. Popular time sources arecrystal oscillators andphase-locked loops.
SoCperipherals includingcounter-timers, real-timetimers andpower-on reset generators. SoCs also includevoltage regulators andpower management circuits.
SoCs comprise manyexecution units. These units must often send data andinstructions back and forth. Because of this, all but the most trivial SoCs requirecommunications subsystems. Originally, as with othermicrocomputer technologies,data bus architectures were used, but recently designs based on sparse intercommunication networks known asnetworks-on-chip (NoC) have risen to prominence and are forecast to overtake bus architectures for SoC design in the near future.[13]
Historically, a shared globalcomputer bus typically connected the different components, also called "blocks" of the SoC.[13] A very common bus for SoC communications is ARM's royalty-free Advanced Microcontroller Bus Architecture (AMBA) standard.
Direct memory access controllers route data directly between external interfaces and SoC memory, bypassing the CPU orcontrol unit, thereby increasing the datathroughput of the SoC. This is similar to somedevice drivers of peripherals on component-basedmulti-chip module PC architectures.
Wire delay is not scalable due to continuedminiaturization,system performance does not scale with the number of cores attached, the SoC'soperating frequency must decrease with each additional core attached for power to be sustainable, and long wires consume large amounts of electrical power. These challenges are prohibitive to supportingmanycore systems on chip.[13]: xiii
In the late 2010s, a trend of SoCs implementingcommunications subsystems in terms of a network-like topology instead ofbus-based protocols has emerged. A trend towards more processor cores on SoCs has caused on-chip communication efficiency to become one of the key factors in determining the overall system performance and cost.[13]: xiii This has led to the emergence of interconnection networks withrouter-basedpacket switching known as "networks on chip" (NoCs) to overcome thebottlenecks of bus-based networks.[13]: xiii
Networks-on-chip have advantages including destination- and application-specificrouting, greater power efficiency and reduced possibility ofbus contention. Network-on-chip architectures take inspiration fromcommunication protocols likeTCP and theInternet protocol suite for on-chip communication,[13] although they typically have fewernetwork layers. Optimal network-on-chipnetwork architectures are an ongoing area of much research interest. NoC architectures range from traditional distributed computingnetwork topologies such astorus,hypercube,meshes andtree networks togenetic algorithm scheduling torandomized algorithms such asrandom walks with branching and randomizedtime to live (TTL).
Many SoC researchers consider NoC architectures to be the future of SoC design because they have been shown to efficiently meet power and throughput needs of SoC designs. Current NoC architectures are two-dimensional. 2D IC design has limitedfloorplanning choices as the number of cores in SoCs increase, so asthree-dimensional integrated circuits (3DICs) emerge, SoC designers are looking towards building three-dimensional on-chip networks known as 3DNoCs.[13]
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A system on a chip consists of both thehardware, described in§ Structure, and the software controlling the microcontroller, microprocessor or digital signal processor cores, peripherals and interfaces. Thedesign flow for an SoC aims to develop this hardware and software at the same time, also known as architectural co-design. The design flow must also take into account optimizations (§ Optimization goals) and constraints.
Most SoCs are developed from pre-qualified hardware componentIP core specifications for the hardware elements andexecution units, collectively "blocks", described above, together with softwaredevice drivers that may control their operation. Of particular importance are theprotocol stacks that drive industry-standard interfaces likeUSB. The hardware blocks are put together usingcomputer-aided design tools, specificallyelectronic design automation tools; thesoftware modules are integrated using a softwareintegrated development environment.
SoCs components are also often designed inhigh-level programming languages such asC++,MATLAB orSystemC and converted toRTL designs throughhigh-level synthesis (HLS) tools such asC to HDL orflow to HDL.[14] HLS products called "algorithmic synthesis" allow designers to use C++ to model and synthesize system, circuit, software and verification levels all in one high level language commonly known tocomputer engineers in a manner independent of time scales, which are typically specified in HDL.[15] Other components can remain software and be compiled and embedded ontosoft-core processors included in the SoC as modules in HDL asIP cores.
Once thearchitecture of the SoC has been defined, any new hardware elements are written in an abstracthardware description language termedregister transfer level (RTL) which defines the circuit behavior, or synthesized into RTL from a high level language through high-level synthesis. These elements are connected together in a hardware description language to create the full SoC design. The logic specified to connect these components and convert between possibly different interfaces provided by different vendors is calledglue logic.
Chips are verified for validation correctness before being sent to asemiconductor foundry. This process is calledfunctional verification and it accounts for a significant portion of the time and energy expended in thechip design life cycle, often quoted as 70%.[16][17] With the growing complexity of chips,hardware verification languages likeSystemVerilog,SystemC,e, and OpenVera are being used.Bugs found in the verification stage are reported to the designer.
Traditionally, engineers have employed simulation acceleration,emulation or prototyping onreprogrammable hardware to verify and debug hardware and software for SoC designs prior to the finalization of the design, known astape-out.Field-programmable gate arrays (FPGAs) are favored for prototyping SoCs becauseFPGA prototypes are reprogrammable, allowdebugging and are more flexible thanapplication-specific integrated circuits (ASICs).[18][19]
With high capacity and fast compilation time, simulation acceleration and emulation are powerful technologies that provide wide visibility into systems. Both technologies, however, operate slowly, on the order of MHz, which may be significantly slower – up to 100 times slower – than the SoC's operating frequency. Acceleration and emulation boxes are also very large and expensive at over US$1 million.[citation needed]
FPGA prototypes, in contrast, use FPGAs directly to enable engineers to validate and test at, or close to, a system's full operating frequency with real-world stimuli. Tools such as Certus[20] are used to insert probes in the FPGA RTL that make signals available for observation. This is used to debug hardware, firmware and software interactions across multiple FPGAs with capabilities similar to a logic analyzer.
In parallel, the hardware elements are grouped and passed through a process oflogic synthesis, during which performance constraints, such as operational frequency and expected signal delays, are applied. This generates an output known as anetlist describing the design as a physical circuit and its interconnections. These netlists are combined with theglue logic connecting the components to produce the schematic description of the SoC as a circuit which can beprinted onto a chip. This process is known asplace and route and precedestape-out in the event that the SoCs are produced asapplication-specific integrated circuits (ASIC).
SoCs must optimizepower use, area ondie, communication, positioning forlocality between modular units and other factors. Optimization is necessarily a design goal of SoCs. If optimization was not necessary, the engineers would use amulti-chip module architecture without accounting for the area use, power consumption or performance of the system to the same extent.
Common optimization targets for SoC designs follow, with explanations of each. In general, optimizing any of these quantities may be a hardcombinatorial optimization problem, and can indeed beNP-hard fairly easily. Therefore, sophisticatedoptimization algorithms are often required and it may be practical to useapproximation algorithms orheuristics in some cases. Additionally, most SoC designs containmultiple variables to optimize simultaneously, soPareto efficient solutions are sought after in SoC design. Oftentimes the goals of optimizing some of these quantities are directly at odds, further adding complexity to design optimization of SoCs and introducingtrade-offs in system design.
For broader coverage of trade-offs andrequirements analysis, seerequirements engineering.
SoCs are optimized to minimize theelectrical power used to perform the SoC's functions. Most SoCs must use low power. SoC systems often require longbattery life (such assmartphones), can potentially spend months or years without a power source while needing to maintain autonomous function, and often are limited in power use by a high number ofembedded SoCs beingnetworked together in an area. Additionally, energy costs can be high and conserving energy will reduce thetotal cost of ownership of the SoC. Finally,waste heat from high energy consumption can damage other circuit components if too much heat is dissipated, giving another pragmatic reason to conserve energy. The amount of energy used in a circuit is theintegral ofpower consumed with respect to time, and theaverage rate of power consumption is the product ofcurrent byvoltage. Equivalently, byOhm's law, power is current squared times resistance or voltage squared divided byresistance:
SoCs are frequently embedded inportable devices such assmartphones,GPS navigation devices, digitalwatches (includingsmartwatches) andnetbooks. Customers want long battery lives formobile computing devices, another reason that power consumption must be minimized in SoCs.Multimedia applications are often executed on these devices, including video games,video streaming,image processing; all of which have grown incomputational complexity in recent years with user demands and expectations for higher-quality multimedia. Computation is more demanding as expectations move towards3D video athigh resolution withmultiple standards, so SoCs performing multimedia tasks must be computationally capable platform while being low power to run off a standard mobile battery.[12]: 3
SoCs are optimized to maximizepower efficiency in performance per watt: maximize the performance of the SoC given a budget of power usage. Many applications such asedge computing,distributed processing andambient intelligence require a certain level ofcomputational performance, but power is limited in most SoC environments.
SoC designs are optimized to minimizewaste heatoutput on the chip. As with otherintegrated circuits, heat generated due to highpower density are thebottleneck to furtherminiaturization of components.[21]: 1 The power densities of high speed integrated circuits, particularly microprocessors and including SoCs, have become highly uneven. Too much waste heat can damage circuits and erodereliability of the circuit over time. High temperatures and thermal stress negatively impact reliability,stress migration, decreasedmean time between failures,electromigration,wire bonding,metastability and other performance degradation of the SoC over time.[21]: 2–9
In particular, most SoCs are in a small physical area or volume and therefore the effects of waste heat are compounded because there is little room for it to diffuse out of the system. Because of hightransistor counts on modern devices, oftentimes a layout of sufficient throughput and hightransistor density is physically realizable fromfabrication processes but would result in unacceptably high amounts of heat in the circuit's volume.[21]: 1
These thermal effects force SoC and other chip designers to apply conservativedesign margins, creating less performant devices to mitigate the risk ofcatastrophic failure. Due to increasedtransistor densities as length scales get smaller, eachprocess generation produces more heat output than the last. Compounding this problem, SoC architectures are usually heterogeneous, creating spatially inhomogeneousheat fluxes, which cannot be effectively mitigated by uniformpassive cooling.[21]: 1
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SoCs are optimized to maximize computational and communicationsthroughput.
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SoCs are optimized to minimizelatency for some or all of their functions. This can be accomplished bylaying out elements with proper proximity andlocality to each-other to minimize the interconnection delays and maximize the speed at which data is communicated between modules,functional units and memories. In general, optimizing to minimize latency is anNP-complete problem equivalent to theBoolean satisfiability problem.
Fortasks running on processor cores, latency and throughput can be improved withtask scheduling. Some tasks run in application-specific hardware units, however, and even task scheduling may not be sufficient to optimize all software-based tasks to meet timing and throughput constraints.
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Systems on chip are modeled with standard hardwareverification and validation techniques, but additional techniques are used to model and optimize SoC design alternatives to make the system optimal with respect tomultiple-criteria decision analysis on the above optimization targets.
Task scheduling is an important activity in any computer system with multipleprocesses orthreads sharing a single processor core. It is important to reduce§ Latency and increase§ Throughput forembedded software running on an SoC's§ Processor cores. Not every important computing activity in a SoC is performed in software running on on-chip processors, but scheduling can drastically improve performance of software-based tasks and other tasks involvingshared resources.
Software running on SoCs often schedules tasks according tonetwork scheduling andrandomized scheduling algorithms.
Hardware and software tasks are often pipelined inprocessor design. Pipelining is an important principle forspeedup incomputer architecture. They are frequently used inGPUs (graphics pipeline) and RISC processors (evolutions of theclassic RISC pipeline), but are also applied to application-specific tasks such asdigital signal processing and multimedia manipulations in the context of SoCs.[12]
SoCs are often analyzed thoughprobabilistic models,queueing networks, andMarkov chains. For instance,Little's law allows SoC states and NoC buffers to be modeled as arrival processes and analyzed throughPoisson random variables andPoisson processes.
SoCs are often modeled withMarkov chains, bothdiscrete time andcontinuous time variants. Markov chain modeling allowsasymptotic analysis of the SoC'ssteady state distribution of power, heat, latency and other factors to allow design decisions to be optimized for the common case.
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SoC chips are typicallyfabricated usingmetal–oxide–semiconductor (MOS) technology.[22] The netlists described above are used as the basis for the physical design (place and route) flow to convert the designers' intent into the design of the SoC. Throughout this conversion process, the design is analyzed with static timing modeling, simulation and other tools to ensure that it meets the specified operational parameters such as frequency, power consumption and dissipation, functional integrity (as described in the register transfer level code) and electrical integrity.
When all known bugs have been rectified and these have been re-verified and all physical design checks are done, the physical design files describing each layer of the chip are sent to the foundry's mask shop where a full set of glass lithographic masks will be etched. These are sent to a wafer fabrication plant to create the SoC dice before packaging and testing.
SoCs can be fabricated by several technologies, including:
ASICs consume less power and are faster than FPGAs but cannot be reprogrammed and are expensive to manufacture. FPGA designs are more suitable for lower volume designs, but after enough units of production ASICs reduce the total cost of ownership.[23]
SoC designs consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. With fewer packages in the system, assembly costs are reduced as well.
However, like mostvery-large-scale integration (VLSI) designs, the total cost[clarification needed] is higher for one large chip than for the same functionality distributed over several smaller chips, because oflower yields[clarification needed] and highernon-recurring engineering costs.
When it is not feasible to construct an SoC for a particular application, an alternative is asystem in package (SiP) comprising a number of chips in a singlepackage. When produced in large volumes, SoC is more cost-effective than SiP because its packaging is simpler.[24] Another reason SiP may be preferred iswaste heat may be too high in a SoC for a given purpose because functional components are too close together, and in an SiP heat will dissipate better from different functional modules since they are physically further apart.
Some examples of systems on a chip are:
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SoCresearch and development often compares many options. Benchmarks, such as COSMIC,[25] are developed to help such evaluations.
In interviews most of the interviewers are asking questions on "What is Difference between Verification and Validation?" Many people use verification and validation interchangeably but both have different meanings.
