Asystem bus is a singlecomputer bus that connects the major components of a computer system,combining the functions of adata bus to carry information, anaddress bus to determine where it should be sent or read from, and acontrol bus to determine its operation. The technique was developed to reduce costs and improve modularity, and although popular in the 1970s and 1980s, more modern computers use a variety of separate buses adapted to more specific needs.

Thesystem level bus (as distinct from a CPU's internaldatapath busses) connects the CPU to memory and I/O devices.^[1]Typically a system level bus is designed for use as abackplane.^[2]

Many of the computers were based on theFirst Draft of a Report on the EDVAC report published in 1945. In what became known as theVon Neumann architecture, a central control unit andarithmetic logic unit (ALU, which he called the central arithmetic part) were combined withcomputer memory andinput and output functions to form astored program computer.^[3] TheReport presented a general organization and theoretical model of the computer, however, not the implementation of that model.^[4]Soon designs integrated the control unit and ALU into what became known as thecentral processing unit (CPU).

Computers in the 1950s and 1960s were generally constructed in an ad-hoc fashion.For example, the CPU, memory, and input/output units were each one or more cabinets connected by cables. Engineers used the common techniques of standardized bundles of wires and extended the concept asbackplanes were used to holdprinted circuit boards in these early machines. The name "bus" was already used for "bus bars" that carried electrical power to the various parts of electric machines, including early mechanical calculators.^[5]The advent ofintegrated circuits vastly reduced the size of each computer unit, and buses became more standardized.^[6]Standard modules could be interconnected in more uniform ways and were easier to develop and maintain.

To provide even more modularity with reduced cost,memory andI/O buses (and the requiredcontrol andpower buses) were sometimes combined into a single unified system bus.^[7]Modularity and cost became important as computers became small enough to fit in a single cabinet (and customers expected similar price reductions).Digital Equipment Corporation (DEC) further reduced cost for mass-producedminicomputers, andmemory-mapped I/O into the memory bus, so that the devices appeared to be memory locations. This was implemented in theUnibus of thePDP-11 around 1969, eliminating the need for a separate I/O bus.^[8]Even computers such as thePDP-8 without memory-mapped I/O were soon implemented with a system bus, which allowed modules to be plugged into any slot.^[9]Some authors called this a new streamlined "model" of computer architecture.^[10]

Many early microcomputers (with a CPU generally on a singleintegrated circuit) were built with a single system bus, starting with theS-100 bus in theAltair 8800 computer system in about 1975.^[11]TheIBM PC used theIndustry Standard Architecture (ISA) bus as its system bus in 1981. The passive backplanes of early models were replaced with the standard of putting the CPU and RAM on amotherboard, with only optionaldaughterboards orexpansion cards in system bus slots.

TheMultibus became a standard of theInstitute of Electrical and Electronics Engineers as IEEE standard 796 in 1983.^[12]Sun Microsystems developed theSBus in 1989 to support smaller expansion cards.^[13]The easiest way to implementsymmetric multiprocessing was to plug in more than one CPU into the shared system bus, which was used through the 1980s.However, the shared bus quickly became the bottleneck and more sophisticated connection techniques were explored.^[14]

Even in very simple systems, at various times the data bus is driven by the program memory, by RAM, and by I/O devices.To preventbus contention on the data bus, at any one instant only one device drives the data bus.In very simple systems, only the data bus is required to be a bidirectional bus.In very simple systems, thememory address register always drives the address bus, thecontrol unit always drives the control bus,and anaddress decoder selects which particular device is allowed to drive the data bus during this bus cycle.In very simple systems, everyinstruction cycle starts with a READ memory cycle where program memory drives the instruction onto the data bus while theinstruction register latches that instruction from the data bus.Some instructions continue with a WRITE memory cycle where thememory data register drives data onto the data bus into the chosen RAM or I/O device.Other instructions continue with another READ memory cycle where the chosen RAM, program memory, or I/O device drives data onto the data bus while the memory data register latches that data from the data bus.

More complex systems have amulti-master bus—not only do they have many devices that each drive the data bus, but also have manybus masters that each drive the address bus.The address bus as well as the data bus inbus snooping systems is required to be a bidirectional bus, often implemented as athree-state bus.To prevent bus contention on the address bus, abus arbiter selects which particular bus master is allowed to drive the address bus during this bus cycle.

Intel has used the termDual Independent Bus (DIB) for two different purposes. The first one came when Intel changed from a singlelocal bus to the DIB, using the externalfront-side bus to the main systemmemory and I/O devices, and the internalback-side bus to the L2CPU cache. This was introduced in thePentium Pro in 1995.^[15][16][17]

In 2005 and 2006 Intel introduced the 8500 and 5000 chipsets, where DIB referred to the twofront-side buses on a chipset, which doubles the system bandwidth compared to having just one FSB shared by all the CPUs. However, the information needed to guarantee thecache coherence of shared data located in different caches have to be sent in broadcast (snooped) to check the other FSB's CPUs' cache state, reducing the available bandwidth. To reduce the coherency traffic, asnoop filter was included in the higher-end chipsets, in order to have cache state information available on-chipset. In 2007 Intel extended the idea of multiple buses in the 7300 chipset with four independent FSBs, calling itdedicated high-speed interconnects (DHSI).^[18]

The system bus approach is obsolete in the modern personal and server computers, which instead use higher-performance interconnection technologies such asHyperTransport andIntel QuickPath Interconnect, while the system bus architecture continued to be used on simpler embedded microprocessors.The systems bus can even be internal to a single integrated circuit, producing asystem-on-a-chip. Examples of on-chip bus includeAMBA,CoreConnect,Wishbone, and modified versions ofPCI orPCIe.^[19]

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Direct Media Interface is an example of a system bus (besides directly accessedPCIE lanes) implemented by Intel and known since at least 2004. It's primarily used to accessmemory-mapped I/O devices and communicate CPU to thechipset.

• Bus (computing)
• External Bus Interface
• Expansion bus

• Computer buses

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