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Asuperscalar processor (ormultiple-issue processor[1]) is aCPU that implements a form ofparallelism calledinstruction-level parallelism within a single processor.[2] In contrast to ascalar processor, which can execute at most one single instruction per clock cycle, a superscalar processor can execute or start executing more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to differentexecution units on the processor. It therefore allows morethroughput (the number of instructions that can be executed in a unit of time which can even be less than 1) than would otherwise be possible at a givenclock rate. Each execution unit is not a separate processor (or a core if the processor is amulti-core processor), but an execution resource within a single CPU such as anarithmetic logic unit.
While a superscalar CPU is typically alsopipelined, superscalar and pipelining execution are considered different performance enhancement techniques. The former (superscalar) executes multiple instructions in parallel by using multiple execution units, whereas the latter (pipeline) executes multiple instructions in the same execution unit in parallel by dividing the execution unit into different phases. In the "Simple superscalar pipeline" figure, fetching two instructions at the same time is superscaling, and fetching the next two before the first pair has been written back is pipelining.
The superscalar technique is traditionally associated with several identifying characteristics (within a given CPU):
Seymour Cray'sCDC 6600 from 1964, while not capable of issuing multiple instructions per cycle, is often cited as an early influence to modern superscalar processors for its ability to execute instructions simultaneously through multiple functional units. The 1967IBM System/360 Model 91, was another early influence that introduced out-of-order execution, pioneering use ofTomasulo's algorithm.[3] TheIntel i960CA (1989),[4] theAMD 29000-series 29050 (1990), and the MotorolaMC88110 (1991),[5] microprocessors were the first commercial single-chip superscalar microprocessors.RISC microprocessors like these were the first to have superscalar execution, because RISC architectures free transistors and die area which can be used to include multiple execution units and the traditional uniformity of the instruction set favors superscalar dispatch (this was why RISC designs were faster thanCISC designs through the 1980s and into the 1990s, and it's far more complicated to do multiple dispatch when instructions have variable bit length).
Except for CPUs used inlow-power applications,embedded systems, andbattery-powered devices, essentially all general-purpose CPUs developed since about 1998 are superscalar.
TheP5 Pentium was the first superscalar x86 processor; theNx586,P6 Pentium Pro andAMD K5 were among the first designs which decodex86-instructions asynchronously into dynamicmicrocode-likemicro-op sequences prior to actual execution on a superscalarmicroarchitecture; this opened up for dynamic scheduling of bufferedpartial instructions and enabled more parallelism to be extracted compared to the more rigid methods used in the simpler P5 Pentium; it also simplifiedspeculative execution and allowed higher clock frequencies compared to designs such as the advancedCyrix 6x86.
The simplest processors are scalar processors. Each instruction executed by a scalar processor typically manipulates one or two data items at a time. By contrast, each instruction executed by avector processor operates simultaneously on many data items. An analogy is the difference betweenscalar and vector arithmetic. A superscalar processor is a mixture of the two. Each instruction processes one data item, but there are multiple execution units within each CPU thus multiple instructions can be processing separate data items concurrently.
Superscalar CPU design emphasizes improving the instruction dispatcher accuracy and allowing it to keep the multiple execution units in use at all times. This has become increasingly important as the number of units has increased. While early superscalar CPUs would have twoALUs and a singleFPU, a later design such as thePowerPC 970 includes four ALUs, two FPUs, and two SIMD units. If the dispatcher is ineffective at keeping all of these units fed with instructions, the performance of the system will be no better than that of a simpler, cheaper design.
A superscalar processor usually sustains an execution rate in excess of oneinstruction per machine cycle. But merely processing multiple instructions concurrently does not make an architecture superscalar, sincepipelined,multiprocessor ormulti-core architectures also achieve that, but with different methods.
In a superscalar CPU the dispatcher reads instructions from memory and decides which ones can be run in parallel, dispatching each to one of the several execution units contained inside a single CPU. Therefore, a superscalar processor can be envisioned as having multiple parallel pipelines, each of which is processing instructions simultaneously from a single instruction thread.
Most modern superscalar CPUs also have logic to reorder the instructions to try to avoid pipeline stalls and increase parallel execution.
Available performance improvement from superscalar techniques is limited by three key areas:
Existing binary executable programs have varying degrees of intrinsic parallelism. In some cases instructions are not dependent on each other and can be executed simultaneously. In other cases they are inter-dependent: one instruction impacts either resources or results of the other. The instructionsa = b + c; d = e + f can be run in parallel because none of the results depend on other calculations. However, the instructionsa = b + c; b = e + f might not be runnable in parallel, depending on the order in which the instructions complete while they move through the units.
Although the instruction stream may contain no inter-instruction dependencies, a superscalar CPU must nonetheless check for that possibility, since there is no assurance otherwise and failure to detect a dependency would produce incorrect results.
No matter how advanced thesemiconductor process or how fast the switching speed, this places a practical limit on how many instructions can be simultaneously dispatched. While process advances will allow ever greater numbers of execution units (e.g. ALUs), the burden of checking instruction dependencies grows rapidly, as does the complexity of register renaming circuitry to mitigate some dependencies. Collectively thepower consumption, complexity and gate delay costs limit the achievable superscalar speedup.
However even given infinitely fast dependency checking logic on an otherwise conventional superscalar CPU, if the instruction stream itself has many dependencies, this would also limit the possible speedup. Thus the degree of intrinsic parallelism in the code stream forms a second limitation.
Collectively, these limits drive investigation into alternative architectural changes such asvery long instruction word (VLIW),explicitly parallel instruction computing (EPIC),simultaneous multithreading (SMT), andmulti-core computing.
With VLIW, the burdensome task of dependency checking byhardware logic at run time is removed and delegated to thecompiler.Explicitly parallel instruction computing (EPIC) is like VLIW with extra cache prefetching instructions.
Simultaneous multithreading (SMT) is a technique for improving the overall efficiency of superscalar processors. SMT permits multiple independent threads of execution to better utilize the resources provided by modern processor architectures. The fact that they are independent means that we know that the instruction of one thread can be executed out of order and/or in parallel with the instruction of a different one. Also, one independent thread will not produce a pipeline bubble in the code stream of a different one, for example, due to a branch.
Superscalar processors differ frommulti-core processors in that the several execution units are not entire processors. A single processor is composed of finer-grained execution units such as theALU,integermultiplier, integer shifter,FPU, etc. There may be multiple versions of each execution unit to enable the execution of many instructions in parallel. This differs from a multi-core processor that concurrently processes instructions frommultiple threads, one thread perprocessing unit (called "core"). It also differs from apipelined processor, where the multiple instructions can concurrently be in various stages of execution,assembly-line fashion.
The various alternative techniques are not mutually exclusive—they can be (and frequently are) combined in a single processor. Thus a multicore CPU is possible where each core is an independent processor containing multiple parallel pipelines, each pipeline being superscalar. Some processors also includevector capability.
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