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| General information | |
|---|---|
| Launched | December 2009 |
| Designed by | Intel Tera-Scale Computing Research Program |
| Performance | |
| Max.CPUclock rate | 1 GHz |
| Cache | |
| L1cache | 16KB per core, 4-way set associative |
| L2 cache | 256KB per core, 4-way set associative |
| Architecture and classification | |
| Technology node | 45 nm transistors |
| Instructions | x86,MIC |
| Physical specifications | |
| Transistors |
|
| Cores |
|
| Memory (RAM) |
|
| Socket |
|
| History | |
| Predecessor | Teraflops Research Chip |
| Successor | Xeon Phi |
TheSingle-Chip Cloud Computer (SCC) is a computer processor created byIntel Corporation in 2009 that features 48 distinct physical cores.[1] These cores communicate through an architecture similar to that of a cloud computer data center. Cores are components of the processor responsible for executing instructions that enable the computer to function. The SCC resulted from an Intel project focusing on researchingmulti-core processors andparallel processing. Intel also aimed to explore the integration of designs and architecture from large cloud computer data centers (cloud computing) into a single processing chip. The name "Single-chip Cloud Computer" reflects this concept.[2]
The SCC is currently utilized for research purposes. It can run theLinux operating system on the chip but it cannot runWindows.[3] Some applications of the SCC includeweb servers,data informatics,bioinformatics, andfinancial analytics.[4]
The cores are spread across the chip but capable of direct communication. The chip comprises 48P54C Pentium cores connected with a 4×6 2D-mesh. This mesh consists of 24 tiles arranged in four rows and six columns. Each tile contains two cores and a 16 KB (8 per core)message passing buffer (MPB) shared by the two cores, essentially functioning as a router.[5] This router enables each core to communicate directly with others, eliminating the need to send information back to the main memory for rerouting to other cores.[3] The SCC contains 1.3 billion45 nmtransistors capable of amplifying signals or acting as a switch, using 25 to 125watts of power depending on processing demand. Each chip includes four DDR3memory controllers connected to the 2D mesh, capable of addressing 64 GB ofrandom-access memory. The DDR3 memory facilitates communication among tiles, contributing to the chip's functionality. These controllers, along with the transistors, manage the activation and deactivation of specific tiles to conserve power when not in use. Proper coding integration results in a functional processor with high speed, power, and energy efficiency, resembling a network of cloud computers.[6]
The SCC comes with RCCE, a simplemessage-passing interface provided by Intel supporting basic message-buffering operations.[5] The SCC operates in two modes: processor mode and mesh mode.
In processor mode, cores are active, executing code from the system memory, and performing programmed I/O (inputs and outputs) through the system connected to the system boardFPGA. Software running on the SCC's embedded management console handles tasks such as loading memory and configuring the processor forbootstrapping (sustaining after the initial load).[7]
In mesh mode, cores are turned off, leaving only the routers, transistors, and RAM controllers active. These components send and receive largepackets of data without amemory map.[7]
Intel intends to share this technology with other companies, includingHP,Yahoo, andMicrosoft, to foster collaborative research on the SCC to advance the technology. The goal is to make the SCC scalable to 100+ cores, potentially achieved by enabling communication between individual chips. Intel aims to enhance parallelprogramming productivity and power management, leveraging the chip's architecture and numerous cores. Further experimentation is planned on this architecture and similar chip architectures to develop many-core scalable processors maximizing processing power while maintaining energy efficiency.[4]
