Radiation hardening is the process of makingelectronic components and circuits resistant to damage or malfunction caused by high levels ofionizing radiation (particle radiation and high-energyelectromagnetic radiation),[1] especially for environments inouter space (especially beyondlow Earth orbit), aroundnuclear reactors andparticle accelerators, or duringnuclear accidents ornuclear warfare.
Mostsemiconductor electronic components are susceptible to radiation damage, andradiation-hardened (rad-hard) components are based on their non-hardened equivalents, with some design and manufacturing variations that reduce the susceptibility to radiation damage. Due to the low demand and the extensive development and testing required to produce a radiation-tolerant design of amicroelectronic chip, the technology of radiation-hardened chips tends to lag behind the most recent developments.[2] They also typically cost more than their commercial counterparts.[2]
Radiation-hardened products are typically tested to one or more resultant-effects tests, including total ionizing dose (TID), enhanced low dose rate effects (ELDRS), neutron and proton displacement damage, and single event effects (SEEs).
Environments with high levels of ionizing radiation create special design challenges. A singlecharged particle can knock thousands ofelectrons loose, causingelectronic noise andsignal spikes. In the case ofdigital circuits, this can cause results which are inaccurate or unintelligible. This is a particularly serious problem in the design ofsatellites,spacecraft, futurequantum computers,[3][4][5]military aircraft, nuclear power stations, andnuclear weapons. In order to ensure the proper operation of such systems, manufacturers ofintegrated circuits andsensors intended for themilitary oraerospace markets employ various methods of radiation hardening. The resulting systems are said to berad(iation)-hardened,rad-hard, or (within context)hardened.
Typical sources of exposure of electronics to ionizing radiation are theVan Allen radiation belts for satellites, nuclear reactors in power plants for sensors and control circuits, particle accelerators for control electronics (particularlyparticle detector devices), residual radiation fromisotopes inchip packaging materials,cosmic radiation for spacecraft and high-altitude aircraft, andnuclear explosions for potentially all military and civilian electronics.
Secondary particles result from interaction of other kinds of radiation with structures around the electronic devices.
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Two fundamental damage mechanisms take place:
Lattice displacement is caused byneutrons, protons, alpha particles, heavy ions, and very high energygamma photons. They change the arrangement of the atoms in thecrystal lattice, creating lasting damage, and increasing the number ofrecombination centers, depleting theminority carriers and worsening the analog properties of the affected semiconductorjunctions. Counterintuitively, higher doses over a short time cause partialannealing ("healing") of the damaged lattice, leading to a lower degree of damage than with the same doses delivered in low intensity over a long time (LDR or low dose rate). This type of problem is particularly significant inbipolar transistors, which are dependent on minority carriers in their base regions; increased losses caused byrecombination cause loss of the transistorgain (seeneutron effects). Components certified as ELDRS (enhanced low dose rate sensitive)-free do not show damage with fluxes below 0.01 rad(Si)/s = 36 rad(Si)/h.
Ionization effects are caused by charged particles, including ones with energy too low to cause lattice effects. The ionization effects are usually transient, creatingglitches and soft errors, but can lead to destruction of the device if they trigger other damage mechanisms (e.g., alatchup).Photocurrent caused byultraviolet and X-ray radiation may belong to this category as well. Gradual accumulation ofholes in the oxide layer inMOSFET transistors leads to worsening of their performance, up to device failure when the dose is high enough (seetotal ionizing dose effects).
The effects can vary wildly depending on all the parameters – type of radiation, total dose and radiation flux, combination of types of radiation, and even the kind of device load (operating frequency, operating voltage, actual state of the transistor during the instant it is struck by the particle) – which makes thorough testing difficult, time-consuming, and requiring many test samples.
The "end-user" effects can be characterized in several groups:
A neutron interacting with a semiconductor lattice will displace the atoms in the lattice. This leads to an increase in the count of recombination centers anddeep-level defects, reducing the lifetime of minority carriers, thus affectingbipolar devices more thanCMOS ones. Bipolar devices onsilicon tend to show changes in electrical parameters at levels of 1010 to 1011 neutrons/cm2, while CMOS devices aren't affected until 1015 neutrons/cm2. The sensitivity of devices may increase together with increasing level of integration and decreasing size of individual structures. There is also a risk of induced radioactivity caused byneutron activation, which is a major source of noise inhigh energy astrophysics instruments. Induced radiation, together with residual radiation from impurities in component materials, can cause all sorts of single-event problems during the device's lifetime.GaAsLEDs, common inoptocouplers, are very sensitive to neutrons. The lattice damage influences the frequency ofcrystal oscillators. Kinetic energy effects (namely lattice displacement) of charged particles belong here too.
Total ionizing dose effects represent the cumulative damage of the semiconductor lattice (lattice displacement damage) caused by exposure to ionizing radiation over time. It is measured inrads and causes slow gradual degradation of the device's performance. A total dose greater than 5000 rads delivered to silicon-based devices in a timespan on the order of seconds to minutes will cause long-term degradation. In CMOS devices, the radiation createselectron–hole pairs in the gate insulation layers,[9] which cause photocurrents during their recombination, and the holes trapped in the lattice defects in the insulator create a persistent gatebiasing and influence the transistors'threshold voltage, making the N-type MOSFET transistors easier and the P-type ones more difficult to switch on. The accumulated charge can be high enough to keep the transistors permanently open (or closed), leading to device failure. Some self-healing takes place over time, but this effect is not too significant. This effect is the same ashot carrier degradation in high-integration high-speed electronics. Crystal oscillators are somewhat sensitive to radiation doses, which alter their frequency. The sensitivity can be greatly reduced by usingswept quartz. Naturalquartz crystals are especially sensitive. Radiation performance curves for TID testing may be generated for all resultant effects testing procedures. These curves show performance trends throughout the TID test process and are included in the radiation test report.
Transient dose effects result from a brief high-intensity pulse of radiation, typically occurring during a nuclear explosion. The high radiation flux creates photocurrents in the entire body of the semiconductor, causing transistors to randomly open, changing logical states offlip-flops andmemory cells. Permanent damage may occur if the duration of the pulse is too long, or if the pulse causes junction damage or a latchup. Latchups are commonly caused by the X-rays and gamma radiation flash of a nuclear explosion. Crystal oscillators may stop oscillating for the duration of the flash due to promptphotoconductivity induced in quartz.
SGEMP effects are caused by the radiation flash traveling through the equipment and causing localionization andelectric currents in the material of the chips,circuit boards,electrical cables and cases.
Single-event effects (SEE) have been studied extensively since the 1970s.[10] When a high-energy particle travels through a semiconductor, it leaves anionized track behind. This ionization may cause a highly localized effect similar to the transient dose one - a benign glitch in output, a less benign bit flip in memory or aregister or, especially inhigh-power transistors, a destructive latchup and burnout. Single event effects have importance for electronics in satellites, aircraft, and other civilian and military aerospace applications. Sometimes, in circuits not involving latches, it is helpful to introduceRCtime constant circuits that slow down the circuit's reaction time beyond the duration of an SEE.
An SET happens when the charge collected from an ionization event discharges in the form of a spurious signal traveling through the circuit. This is de facto the effect of anelectrostatic discharge. it is considered a soft error, and is reversible.
Single-event upsets (SEU) ortransient radiation effects in electronics are state changes of memory or register bits caused by a single ion interacting with the chip. They do not cause lasting damage to the device, but may cause lasting problems to a system which cannot recover from such an error. It is otherwise a reversible soft error. In very sensitive devices, a single ion can cause amultiple-bit upset (MBU) in several adjacent memory cells. SEUs can becomesingle-event functional interrupts (SEFI) when they upset control circuits, such asstate machines, placing the device into an undefined state, atest mode, or a halt, which would then need areset or apower cycle to recover.
An SEL can occur in any chip with aparasitic PNPN structure. A heavy ion or a high-energy proton passing through one of the two inner-transistor junctions can turn on thethyristor-like structure, which then stays "shorted" (an effect known aslatch-up) until the device is power-cycled. As the effect can happen between the power source and substrate, destructively high current can be involved and the part may fail. This is a hard error, and is irreversible. Bulk CMOS devices are most susceptible.
A single-event snapback is similar to an SEL but not requiring the PNPN structure, and can be induced in N-channel MOS transistors switching large currents, when an ion hits near the drain junction and causesavalanche multiplication of thecharge carriers. The transistor then opens and stays opened, a hard error which is irreversible.
An SEB may occur in power MOSFETs when the substrate right under the source region gets forward-biased and the drain-source voltage is higher than the breakdown voltage of the parasitic structures. The resulting high current and local overheating then may destroy the device. This is a hard error, and is irreversible.
SEGR are observed in power MOSFETs when a heavy ion hits the gate region while a high voltage is applied to the gate. A local breakdown then happens in the insulating layer ofsilicon dioxide, causing local overheating and destruction (looking like a microscopicexplosion) of the gate region. It can occur even inEEPROM cells during write or erase, when the cells are subjected to a comparatively high voltage. This is a hard error, and is irreversible.
While proton beams are widely used for SEE testing due to availability, at lower energies proton irradiation can often underestimate SEE susceptibility. Furthermore, proton beams expose devices to risk of total ionizing dose (TID) failure which can cloud proton testing results or result in premature device failure. White neutron beams—ostensibly the most representative SEE test method—are usually derived from solid target-based sources, resulting in flux non-uniformity and small beam areas. White neutron beams also have some measure of uncertainty in their energy spectrum, often with high thermal neutron content.
The disadvantages of both proton and spallation neutron sources can be avoided by using mono-energetic 14 MeV neutrons for SEE testing. A potential concern is that mono-energetic neutron-induced single event effects will not accurately represent the real-world effects of broad-spectrum atmospheric neutrons. However, recent studies have indicated that, to the contrary, mono-energetic neutrons—particularly 14 MeV neutrons—can be used to quite accurately understand SEE cross-sections in modern microelectronics.[11]
Hardened chips are often manufactured oninsulatingsubstrates instead of the usualsemiconductor wafers. Silicon on insulator (SOI) and silicon onsapphire (SOS) are commonly used. While normal commercial-grade chips can withstand between 50 and 100gray (5 and 10 krad), space-grade SOI and SOS chips can survive doses between 1000 and 3000gray (100 and 300 krad).[12][13] At one time many4000 series chips were available in radiation-hardened versions (RadHard).[14] While SOI eliminates latchup events, TID and SEE hardness are not guaranteed to be improved.[15]
Choosing a substrate with wideband gap gives it higher tolerance to deep-level defects; e.g.silicon carbide orgallium nitride.[citation needed]
Use of a specialprocess node provides increased radiation resistance.[16] Due to the high development costs of new radiation hardened processes, the smallest "true" rad-hard (RHBP,rad-hard by process) process is 150 nm as of 2016, however, rad-hard 65 nm FPGAs were available that used some of the techniques used in "true" rad-hard processes (RHBD,rad-hard by design).[17] As of 2019 110 nm rad-hard processes are available.[18]
Bipolar integrated circuits generally have higher radiation tolerance than CMOS circuits. The low-power Schottky (LS)5400 series can withstand 1000 krad, and manyECL devices can withstand 10,000 krad.[14] Usingedgeless CMOS transistors, which have an unconventional physical construction, together with an unconventional physical layout, can also be effective.[19]
MagnetoresistiveRAM, orMRAM, is considered a likely candidate to provide radiation hardened, rewritable, non-volatile conductor memory. Physical principles and early tests suggest that MRAM is not susceptible to ionization-induced data loss.[20]
Capacitor-basedDRAM is often replaced by more rugged (but larger, and more expensive)SRAM. SRAM cells have more transistors per cell than usual (which is 4T or 6T), which makes the cells more tolerant to SEUs at the cost of higher power consumption and size.[21][17]
Shielding the package againstradioactivity is straightforward to reduce exposure of the bare device.[22]
To protect against neutron radiation and theneutron activation of materials, it is possible to shield the chips themselves by use ofdepleted boron (consisting only of isotope boron-11) in theborophosphosilicate glasspassivation layer protecting the chips, as naturally prevalent boron-10 readilycaptures neutrons and undergoesalpha decay (seesoft error).
Error correcting code memory (ECC memory) uses redundant bits to check for and possibly correct corrupted data. Since radiation's effects damage the memory content even when the system is not accessing the RAM, a "scrubber" circuit must continuously sweep the RAM; reading out the data, checking the redundant bits for data errors, then writing back any corrections to the RAM.
Redundant elements can be used at the system level. Three separatemicroprocessor boards may independently compute an answer to a calculation and compare their answers. Any system that produces a minority result will recalculate. Logic may be added such that if repeated errors occur from the same system, that board is shut down.
Redundant elements may be used at the circuit level.[23] A single bit may be replaced with three bits and separate "voting logic" for each bit to continuously determine its result (triple modular redundancy). This increases area of a chip design by a factor of 5, so must be reserved for smaller designs. But it has the secondary advantage of also being "fail-safe" in real time. In the event of a single-bit failure (which may be unrelated to radiation), the voting logic will continue to produce the correct result without resorting to awatchdog timer. System level voting between three separate processor systems will generally need to use some circuit-level voting logic to perform the votes between the three processor systems.
Hardened latches may be used.[24]
A watchdog timer will perform a hard reset of a system unless some sequence is performed that generally indicates the system is alive, such as a write operation from an onboard processor. During normal operation, software schedules a write to the watchdog timer at regular intervals to prevent the timer from running out. If radiation causes the processor to operate incorrectly, it is unlikely the software will work correctly enough to clear the watchdog timer. The watchdog eventually times out and forces a hard reset to the system. This is considered a last resort to other methods of radiation hardening.
Radiation-hardened and radiation tolerant components are often used in military and aerospace applications, including point-of-load (POL) applications, satellite system power supplies, step downswitching regulators,microprocessors,FPGAs,[25] FPGA power sources, and high efficiency, low voltage subsystem power supplies.
However, not all military-grade components are radiation hardened. For example, the USMIL-STD-883 features many radiation-related tests, but has no specification for single event latchup frequency. TheFobos-Grunt space probe may have failed due to a similar assumption.[15]
The market size for radiation hardened electronics used in space applications was estimated to be $2.35 billion in 2021. A new study has estimated that this will reach approximately $4.76 billion by the year 2032.[26][27]
Intelecommunication, the termnuclear hardness has the following meanings:1) an expression of the extent to which the performance of asystem, facility, or device is expected to degrade in a given nuclear environment, 2) the physical attributes of a system orelectronic component that will allow survival in an environment that includesnuclear radiation and electromagnetic pulses (EMP).
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