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TheR4200 is amicroprocessor designed byMIPS Technologies, Inc. (MTI) that implemented theMIPS IIIinstruction set architecture (ISA). It was also known as the VRX during development. The microprocessor was licensed toNEC, and the company fabricated and marketed it as the VR4200. The first VR4200, an 80 MHz part, was introduced in 1993. A faster 100 MHz part became available in 1994.
The R4200 was at least in part intended for use in low-powerWindows NT computers such as personal computers and laptops,[1]: 468 reportedly offering "Pentium processor performance at a tenth of the price", having initially aimed to deliver twice the performance of a 66 MHz Intel486DX2 processor. Reported SPECint benchmark results put the microprocessor's integer performance at around 85% of a P5-variantPentium microprocessor, with floating-point performance being about half that of the Pentium. Expected to be used in Nintendo's "new machine due in 1995",[1] the R4300i variant was used in the widely popularNintendo 64video game console and SNK’sHyper Neo Geo 64 arcade board. The R4200 ultimately did not see any use in personal computers and was repositioned as an embedded microprocessor that competed with theR4600.
The R4200 is ascalar design with a five-stageclassic RISC pipeline. A notable feature is the use of the integerdatapath for performing arithmetic operations on themantissa portion of afloating point number. A separate datapath was used for the exponent. This scheme reduced cost by reducing the number oftransistors, the size of the chip, and power consumption. It also impactedfloating point performance negatively, but the R4200's intended applications did not require high floating point performance.
The R4200 has a 16 kB instructioncache and an 8 kB data cache. Both caches aredirect-mapped. The instruction cache has a 32-byte line size, whereas the data cache has 16-byte line size. The data cache uses thewrite-back write protocol.
The R4200 has a 32-entrytranslation lookaside buffer (TLB) for data, and a 4-entry TLB for instructions. A 33-bitphysical address is supported. Thesystem bus is 64 bits wide and operates at half the internal clock frequency.
The R4200 contained 1.3 million transistors and had an area of 81 mm2. NEC fabricated the R4200 in a600 nmCMOS process with three levels of interconnect. It was packaged in a 179-pinceramic pin grid array that was compatible with theR4x00PC andR4600, or a 208-pinplastic quad flat pack (PQFP). It used a 3.3 V power supply, dissipating 1.8 W typically and a maximum of 2 W at 80 MHz.
In comparison to the Pentium,SPECint ratings had the Pentium at 64.5 and the R4200 at 55.SPECfp ratings had the Pentium at 56 versus the R4200 at 30.[2]
The R4300i is a derivative of the R4200 designed by MTI for embedded applications announced on 17 April 1995.[3] It differs from the R4200 by featuring an improved integer multiplier with a lower latency and a cut-down 32-bit system bus for reduced cost. The chip had an area of 45 mm2 and was fabricated in a350 nm process. By employing multiplexed address and data lines, it could be packaged in a low-cost 120-pin PQFP. It uses a 3.3 V power supply and dissipates 1.5 W running at 40 MHz (80 MHz internally),[4] 1.8 W at 100 MHz and 2.2 W at 133 MHz.
The R4300i was licensed to NEC andToshiba, and was marketed by those companies as the VR4300 or TX4300, respectively. Both companies offered 100 and 133 MHz versions. A derivative of the VR4300 was developed by NEC for theNintendo 64 game console, clocked at 93.75 MHz and labeled NUS-CPU. Although development boards for the Nintendo 64 used stock NEC VR4300 CPUs, the final CPU has been found to be not pin-compatible. This singular use of a MIPS implementation produced significant royalties for MTI, sales for NEC, and made MIPS the highest volume mixed 32/64-bit RISC ISA in 1997.[citation needed]
NEC produced two other derivatives of the R4300 for the general embedded market, the VR4305 and VR4310, announced on 20 January 1998.[5] The VR4310 was available at 100, 133 or 167 MHz. It was manufactured in a250 nm process and packaged in a 120-pin PQFP.
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