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ThePowerPC e5500 is a64-bitPower ISA-basedmicroprocessorcore fromFreescale Semiconductor. The core implements most[1] of the core of thePower ISA v.2.06 withhypervisor support, but notAltiVec. It has a four issue, seven-stageout-of-orderpipeline with adouble precisionFPU, threeInteger units, 32/32 KB data and instruction L1caches, 512 KB private L2 cache per core and up to 2 MB shared L3 cache. Speeds range up to 2.5 GHz, and the core is designed to be highly configurable via theCoreNet fabric and meet the specific needs ofembedded applications with features likemulti-core operation and interface for auxiliary application processing units (APU).
The e5500 is based on thee500mc core and adds some new instructions introduced in the Power ISA 2.06 specification, namely some byte- and bit-level acceleration; Parity, Population count, Bit permute and Compare byte. The FPU is taken straight from thePowerPC e600 core, which is a classic fully pipelined dual precisionIEEE 754 unit running at full core speed and supports conversion between 64-bit floats and integers, effectively twice as fast as the FPU in e500mc. The e5500 also introduces an enhancedbranch prediction unit with an 8-entry link stack.
The e5500 core is the first 64-bit Power ISA core designed solely by Freescale and was introduced at Freescale Technology Forum in June 2010. Simulated models were available in July 2010, hard samples in late 2010 and full scale manufacturing the second half of 2011.Freescale have used thee700 andNG-64 monikers to refer to a very similarly specced core since 2004, but they are not the same product.[2]
e5500 powers the high-performanceQorIQ P5system on a chip (SoC) family which share the common naming scheme: "P50x0".BAE Systems has builtradiation hardened SoCs for devices in space usingRAD5500 cores, based on the e5500 core design.[3]