Indigital signal processing (DSP),parallel processing is a technique duplicating function units to operate different tasks (signals) simultaneously.^[1] Accordingly, we can perform the same processing for differentsignals on the corresponding duplicated function units. Further, due to the features ofparallel processing, the parallel DSP design often contains multiple outputs, resulting in higher throughput than not parallel.

Consider a function unit (${\displaystyle F_0}$) and three tasks (${\displaystyle T_0}$,${\displaystyle T_1}$, and${\displaystyle T_2}$). The required time for the function unit${\displaystyle F_0}$ to process those tasks is${\displaystyle t_0}$,${\displaystyle t_1}$, and${\displaystyle t_2}$, respectively. Then, if we operate these three tasks in a sequential order, the required time to complete them is${\displaystyle t_0+t_1+t_2}$.

However, if we duplicate the function unit to another two copies (${\displaystyle F}$), the aggregate time is reduced to${\displaystyle max(t_0,t_1,t_2)}$, which is smaller than in a sequential order.

Mechanism:

• Parallel: duplicated function units working in parallel
  • Each task is processed entirely by a different function unit.
• Pipelining: different function units working in parallel
  • Each task is split into a sequence of sub-tasks, which are handled by specialized and different function units.

Objective:

• Pipelining leads to a reduction in the critical path, which can increase thesample speed or reducepower consumption at the same speed, yielding higherperformance per watt.
• Parallel processing techniques require multiple outputs, which are computed in parallel in aclock period. Therefore, the effective sample speed is increased by the level of parallelism.

Consider a condition that we are able to apply both parallel processing and pipelining techniques, it is better to choose parallel processing techniques with the following reasons

• Pipelining usually causes I/O bottlenecks
• Parallel processing is also utilized for reduction of power consumption while using slow clocks
• The hybrid method of pipelining and parallel processing further increase the speed of the architecture

Consider a 3-tap FIR filter:^[2]

${\displaystyle y(n)=ax(n)+bx(n-1)+cx(n-2)}$

which is shown in the following figure.

Assume the calculation time for multiplication units is T_m and T_a for add units. The sample period is given by

${\displaystyle T_{\text{sample}}\ge T_m+2T_a}$

By parallelizing it, the resultant architecture is shown as follows. The sample rate now becomes

${\displaystyle T_{\text{sample}}\ge \frac{T_{\text{clock}}}{N}=\frac{T_m+2T_a}{3}}$

where N represents the number of copies.

Please note that, in a parallel system,${\displaystyle T_{\text{sample}}\ne T_{\text{clock}}}$ while${\displaystyle T_{\text{sample}}=T_{\text{clock}}}$ holds in a pipelined system.

Consider the transfer function of a 1st-order IIR filter formulated as

${\displaystyle H(z)=\frac{z^{-1}}{1-a{z}^{-1}}}$

where |a| ≤ 1 for stability, and such filter has only one pole located atz = a;

The corresponding recursive representation is

${\displaystyle y(n+1)=ay(n)+u(n)}$

Consider the design of a 4-parallel architecture (N = 4). In such parallel system, each delay element means a block delay and the clock period is four times the sample period.

Therefore, by iterating the recursion withn = 4k, we have

${\displaystyle y(n+4)=a^{4}y(n)+a^{3}u(n)+a^{2}u(n+1)+au(n+2)+u(n+3)}$

${\displaystyle \to y(4k+4)=a^{4}y(4k)+a^{3}u(4k)+a^{2}u(4k+1)+au(4k+2)+u(4k+3)}$

The corresponding architecture is shown as follows.

The resultant parallel design has the following properties.

• The pole of the original filter is atz = a while the pole for the parallel system is atz = a⁴ which is closer to the origin.
• The pole movement improves the robustness of the system to the round-off noise.
• Hardware complexity of this architecture:N×N multiply-add operations.

The square increase in hardware complexity can be reduced by exploiting the concurrency and the incremental computation to avoid repeated computing.

Another advantage for the parallel processing techniques is that it can reduce the power consumption of a system by reducing the supply voltage.

Consider the following power consumption in a normal CMOS circuit.

${\displaystyle P_{\text{seq}}=C_{\text{total}}\cdot V_0^2\cdot f}$

where theC_total represents the total capacitance of the CMOS circuit.

For a parallel version, the charging capacitance remains the same but the total capacitance increases byN times.

In order to maintain the same sample rate, the clock period of theN-parallel circuit increases toN times the propagation delay of the original circuit.

It makes the charging time prolongsN times. The supply voltage can be reduced toβV₀.

Therefore, the power consumption of the N-parallel system can be formulated as

${\displaystyle P_{\text{para}}=(N{C}_{\text{total}})\cdot (\beta V_0^2)\cdot \frac{f}{N}={\beta }^2{P}_{\text{seq}}}$

whereβ can be computed by

${\displaystyle N(\beta V_0-V_t{)}^2=\beta (V_0-V_t{)}^2.}$

• Digital signal processing
• Parallel computing