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Page (computer memory)

From Wikipedia, the free encyclopedia
Fixed-length contiguous block of virtual memory
Not to be confused withBank (computer memory) orBlock (computer memory).
For broader coverage of this topic, seeMemory paging.

Apage,memory page, orvirtual page is a fixed-length contiguous block ofvirtual memory, described by a single entry in apage table. It is the smallest unit of data for memory management in anoperating system that uses virtual memory. Similarly, apage frame is the smallest fixed-length contiguous block ofphysical memory into which memory pages are mapped by the operating system.[1][2][3]

A transfer of pages between main memory and an auxiliary store, such as ahard disk drive, is referred to aspaging or swapping.[4]

Explanation

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Computer memory is divided into pages so that information can be found more quickly.

The concept is named by analogy to the pages of a printed book. If a reader wanted to find, for example, the 5,000th word in the book, they could count from the first word. This would be time-consuming. It would be much faster if the reader had a listing of how many words are on each page. From this listing they could determine which page the 5,000th word appears on, and how many words to count on that page. This listing of the words per page of the book is analogous to apage table of a computerfile system.[5]

Page size

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"Page size" redirects here. For information on paper, seePaper size.

Page size trade-off

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See also:Page Size Extension
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Page size is usually determined by the processor architecture. Traditionally, pages in a system had uniform size, such as 4,096bytes. However, processor designs often allow two or more, sometimes simultaneous, page sizes due to its benefits. There are several points that can factor into choosing the best page size.[6]

Page table size

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A system with a smaller page size uses more pages, requiring apage table that occupies more space. For example, if a 232 virtualaddress space is mapped to 4 KiB (212 bytes) pages, the number of virtual pages is 220 = (232 / 212). However, if the page size is increased to 32 KiB (215 bytes), only 217 pages are required. A multi-level paging algorithm can decrease the memory cost of allocating a large page table for each process by further dividing the page table up into smaller tables, effectively paging the page table.

TLB usage

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Since every access to memory must be mapped from virtual to physical address, reading the page table every time can be quite costly. Therefore, a very fast kind of cache, thetranslation lookaside buffer (TLB), is often used. The TLB is of limited size, and when it cannot satisfy a given request (aTLB miss) the mapping must be fetched from the page table (either by hardware, firmware, or software, depending on the architecture) for the correct mapping. Larger page sizes mean that a TLB cache of the same size can keep track of larger amounts of memory, which avoids costly TLB misses.

Internal fragmentation

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Rarely do processes require the use of an exact number of pages. As a result, the last page will likely only be partially full, wasting some amount of memory. Larger page sizes lead to a large amount of wasted memory, as more potentially unused portions of memory are loaded into the main memory. Smaller page sizes ensure a closer match to the actual amount of memory required in an allocation.

As an example, assume the page size is 1024 B. If a process allocates 1025 B, two pages must be used, resulting in 1023 B of unused space (where one page fully consumes 1024 B and the other only 1 B).

Disk access

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When transferring from a rotational disk, much of the delay is caused by seek time, the time it takes to correctly position the read/write heads above the disk platters. Because of this, large sequential transfers are more efficient than several smaller transfers. Transferring the same amount of data from disk to memory often requires less time with larger pages than with smaller pages.

Getting page size programmatically

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Most operating systems allow programs to discover the page size atruntime. This allows programs to use memory more efficiently by aligning allocations to this size and reducing overall internal fragmentation of pages.

Unix-like operating systems

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Unix-like systems may use the system functionsysconf(),[7][8][9][10][11] as illustrated in the following example written inthe C programming language.

#include<stdio.h>#include<unistd.h> /* sysconf(3) */intmain(void){printf("The page size for this system is %ld bytes.\n",sysconf(_SC_PAGESIZE));/* _SC_PAGE_SIZE is OK too. */return0;}

In many Unix-like systems, the command-line utilitygetconf can be used.[12][13][14]For example,getconf PAGESIZE will return the page size in bytes.

Windows-based operating systems

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Win32-based operating systems, such as those in theWindows 9x andWindows NT families, may use the system functionGetSystemInfo()[15][16] fromkernel32.dll.

#include<stdio.h>#include<windows.h>intmain(void){SYSTEM_INFOsi;GetSystemInfo(&si);printf("The page size for this system is %u bytes.\n",si.dwPageSize);return0;}

Multiple page sizes

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Someinstruction set architectures can support multiple page sizes, including pages significantly larger than the standard page size. The available page sizes depend on the instruction set architecture, processor type, and operating (addressing) mode. The operating system selects one or more sizes from the sizes supported by the architecture. Note that not all processors implement all defined larger page sizes. This support for larger pages (known as "huge pages" inLinux, "superpages" inFreeBSD, and "large pages" inMicrosoft Windows andIBM AIX terminology) allows for "the best of both worlds", reducing the pressure on theTLB cache (sometimes increasing speed by as much as 15%) for large allocations while still keeping memory usage at a reasonable level for small allocations.

Page sizes among architectures[17]
ArchitectureSmallest page sizeLarger page sizes
IA-32 (32-bitx86)[18]4 KiBMiB inPSE mode, 2 MiB inPAE mode[19]
x86-64[18]4 KiB2 MiB, 1 GiB (only when the CPU hasPDPE1GB flag)
IA-64 (Itanium)[20]4 KiB8 KiB, 64 KiB, 256 KiB, 1 MiB, 4 MiB, 16 MiB, 256 MiB[19]
Power ISA[21]4 KiB64 KiB, 16 MiB, 16 GiB
SPARC v8 with SPARC Reference MMU[22]4 KiB256 KiB, 16 MiB
UltraSPARC Architecture 2007[23]8 KiB64 KiB, 512 KiB (optional), 4 MiB, 32 MiB (optional), 256 MiB (optional), 2 GiB (optional), 16 GiB (optional)
ARMv7[24]4 KiB64 KiB, 1 MiB ("section"), 16 MiB ("supersection") (defined by a particular implementation)
AArch64[25]4 KiB16 KiB, 64 KiB, 2 MiB, 32 MiB, 512 MiB, 1 GiB
RISCV32[26]4 KiB4 MiB ("megapage")
RISCV64[26]4 KiB2 MiB ("megapage"), 1 GiB ("gigapage"), 512 GiB ("terapage", only for CPUs with 43-bit address space or more), 256 TiB ("petapage", only for CPUs with 57-bit address space or more),

Starting with thePentium Pro, and theAMD Athlon,x86 processors support 4 MiB pages (calledPage Size Extension) (2 MiB pages if usingPAE) in addition to their standard 4 KiB pages; newerx86-64 processors, such asAMD's newer AMD64 processors andIntel'sWestmere[27] and laterXeon processors can use 1 GiB pages inlong mode.IA-64 supports as many as eight different page sizes, from 4 KiB up to 256 MiB, and some other architectures have similar features.[specify]

Larger pages, despite being available in the processors used in most contemporarypersonal computers, are not in common use except in large-scale applications, the applications typically found in large servers and incomputational clusters, and in the operating system itself. Commonly, their use requires elevated privileges, cooperation from the application making the large allocation (usually setting a flag to ask the operating system for huge pages), or manual administrator configuration; operating systems commonly, sometimes by design, cannot page them out to disk.

However,SGI IRIX has general-purpose support for multiple page sizes. Each individual process can provide hints and the operating system will automatically use the largest page size possible for a given region of address space.[28] Later work proposed transparent operating system support for using a mix of page sizes for unmodified applications through preemptible reservations, opportunistic promotions, speculative demotions, and fragmentation control.[29]

Linux has supported huge pages on several architectures since the 2.6 series via thehugetlbfs filesystem[30] and withouthugetlbfs since 2.6.38.[31]Windows Server 2003 (SP1 and newer),Windows Vista andWindows Server 2008 support huge pages under the name of large pages.[32]Windows 2000 andWindows XP support large pages internally, but do not expose them to applications.[33] Reserving large pages under Windows requires a corresponding right that thesystem administrator must grant to the user because large pages cannot be swapped out under Windows. Beginning with version 9,Solaris supports large pages onSPARC and x86.[34][35]FreeBSD 7.2-RELEASE features superpages.[36] Note that until recently in Linux, applications needed to be modified in order to use huge pages. The 2.6.38 kernel introduced support for transparent use of huge pages.[31] On Linux kernels supporting transparent huge pages, as well as FreeBSD andSolaris, applications take advantage of huge pages automatically, without the need for modification.[36]

See also

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References

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  1. ^Christopher Kruegel (2012-12-03)."Operating Systems (CS170-08 course)"(PDF).cs.ucsb.edu.Archived(PDF) from the original on 2016-08-10. Retrieved2016-06-13.
  2. ^Martin C. Rinard (1998-08-22)."Operating Systems Lecture Notes, Lecture 9. Introduction to Paging".people.csail.mit.edu. Archived fromthe original on 2016-06-01. Retrieved2016-06-13.
  3. ^"Virtual Memory: pages and page frames".cs.miami.edu. 2012-10-31. Archived fromthe original on 2016-06-11. Retrieved2016-06-13.
  4. ^Belzer, Jack; Holzman, Albert G.; Kent, Allen, eds. (1981), "Virtual memory systems",Encyclopedia of computer science and technology, vol. 14, CRC Press, p. 32,ISBN 0-8247-2214-0
  5. ^Kazemi, Darius (2019-01-11)."RFC-11".365 RFCs.
  6. ^Weisberg, P.; Wiseman, Y. (2009-08-10).Using 4KB Page Size for Virtual Memory is Obsolete. 2009 IEEE International Conference on Information Reuse & Integration.CiteSeerX 10.1.1.154.2023.doi:10.1109/IRI.2009.5211562.
  7. ^limits.h – Base Definitions Reference,The Single UNIX Specification, Version 5 fromThe Open Group
  8. ^sysconf – System Interfaces Reference,The Single UNIX Specification, Version 5 fromThe Open Group
  9. ^sysconf(3) – Linux Library FunctionsManual
  10. ^sysconf(3) – Darwin andmacOS Library FunctionsManual
  11. ^sysconf(3C) – Solaris 11.4 Basic Library Functions ReferenceManual
  12. ^getconf – Shell and Utilities Reference,The Single UNIX Specification, Version 5 fromThe Open Group
  13. ^getconf(1) – Linux User CommandsManual
  14. ^getconf(1) – Darwin andmacOS General CommandsManual
  15. ^"GetSystemInfo function". Microsoft. 2021-10-13.
  16. ^"SYSTEM_INFO structure". Microsoft. 2022-09-23.
  17. ^"Hugepages - Debian Wiki". Wiki.debian.org. 2011-06-21. Retrieved2014-02-06.
  18. ^ab"Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide"(PDF). December 2016. p. 4-2.
  19. ^ab"Documentation/vm/hugetlbpage.txt".Linux kernel documentation. kernel.org. Retrieved2014-02-06.
  20. ^"Intel Itanium Architecture Software Developer's Manual Volume 2: System Architecture"(PDF). May 2010. p. 2:58.
  21. ^IBM Power Systems Performance Guide: Implementing and Optimizing. IBM Redbooks. February 2013.ISBN 978-0-7384-3766-8. Retrieved2014-03-17.
  22. ^"The SPARC Architecture Manual, Version 8". 1992. p. 249.
  23. ^"UltraSPARC Architecture 2007"(PDF). 2010-09-27. p. 427.
  24. ^"ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition".Arm. 2014-05-20. p. B3-1324.
  25. ^"Translation granule".Learn the architecture - AArch64 memory management.Arm. Retrieved2022-08-19.
  26. ^abWaterman, Andrew;Asanović, Krste; Hauser, John (2021).The RISC-V Instruction Set Manual Volume II: Privileged Architecture(PDF). pp. 79–87.
  27. ^"The Intel Xeon 5670: Six Improved Cores". AnandTech. Archived fromthe original on 2010-03-31. Retrieved2012-11-03.
  28. ^"General Purpose Operating System Support for Multiple Page Sizes"(PDF).static.usenix.org. Retrieved2012-11-02.
  29. ^Navarro, Juan; Iyer, Sitararn; Druschel, Peter; Cox, Alan (December 2002).Practical, Transparent Operating System Support for Superpages(PDF). 5th Usenix Symposium on Operating Systems Design and Implementation.
  30. ^"Pages - dankwiki, the wiki of nick black". Retrieved2023-06-17.
  31. ^abCorbet, Jonathan."Transparent huge pages in 2.6.38". LWN. Retrieved2011-03-02.
  32. ^"Large-Page Support".Microsoft Docs. 2018-05-08.
  33. ^"AGP program may hang when using page size extension on Athlon processor". Support.microsoft.com. 2007-01-27. Retrieved2012-11-03.
  34. ^"Supporting Multiple Page Sizes in the Solaris Operating System"(PDF).Sun BluePrints Online. Sun Microsystems. Archived fromthe original(PDF) on 2006-03-12. Retrieved2008-01-19.
  35. ^"Supporting Multiple Page Sizes in the Solaris Operating System Appendix"(PDF).Sun BluePrints Online. Sun Microsystems. Archived fromthe original(PDF) on 2007-01-01. Retrieved2008-01-19.
  36. ^ab"FreeBSD 7.2-RELEASE Release Notes". FreeBSD Foundation. Retrieved2009-05-03.
  37. ^"2.3.1 Read-Only Memory / 2.3.2 Program Random Access Memory".MCS-4 Assembly Language Programming Manual - The INTELLEC 4 Microcomputer System Programming Manual(PDF) (Preliminary ed.). Santa Clara, California, USA:Intel Corporation. December 1973. pp. 2-3 –2-4. MCS-030-1273-1.Archived(PDF) from the original on 2020-03-01. Retrieved2020-03-02.[…] ROM is further divided into pages, each of which contains 256 bytes. Thus locations 0 through 255 comprise page 0 of ROM, location 256 through 511 comprise page 1 and so on. […] Program random access memory (RAM) is organized exactly like ROM. […]
  38. ^ab"1. Introduction: Segment Alignment".8086 Family Utilities - User's Guide for 8080/8085-Based Development Systems(PDF). Revision E (A620/5821 6K DD ed.). Santa Clara, California, USA:Intel Corporation. May 1982 [1980, 1978]. p. 1-6. Order Number: 9800639-04.Archived(PDF) from the original on 2020-02-29. Retrieved2020-02-29.

Further reading

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  • Dandamudi, Sivarama P. (2003).Fundamentals of Computer Organization and Design (1st ed.).Springer. pp. 740–741.ISBN 0-387-95211-X.
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